Efficient Decompositional Model Checking for Regular Timing Diagrams

Amla, Nina; Emerson, E. Allen; Namjoshi, Kedar S.

doi:10.1007/3-540-48153-2_7

Cited by 14 publications

(13 citation statements)

References 22 publications

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“…The original work on the efficiency of verifying weak automata is due to Bloem, Ravi and Somenzi [5]. Other timing diagram formalizations have supported some of the language extensions discussed here [2,6,12], but none related the diagrammatic features of these languages to efficiency in verification.…”

Section: Related Workmentioning

confidence: 99%

Towards Diagrammability and Efficiency in Event Sequence Languages

Fisler¹

2003

Lecture Notes in Computer Science

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Abstract. Many industrial verification teams are developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardware specific, as well as efficient to verify. While the formal verification community has formal models for assessing the efficiency of an event sequence language, none of these models also accounts for designer friendliness. We propose an intermediate language for event sequences that addresses both concerns. The language achieves usability through a correlation to timing diagrams; its efficiency arises from its mapping into deterministic weak automata. We present the language, relate it to existing event sequence languages, and prove its relationship to deterministic weak automata. These results indicate that timing diagrams can become more expressive while remaining more efficient for symbolic model checking than LTL.

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Section: Related Workmentioning

confidence: 99%

Towards Diagrammability and Efficiency in Event Sequence Languages

Fisler¹

2003

Lecture Notes in Computer Science

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“…Each node in an MTD contains a Regular Timing Diagram (RTD) [AEN99]. Section 2.1 presents the formal definitions of both MTD's and RTD's.…”

Section: Modular Timing Diagramsmentioning

confidence: 99%

“…This DFA just checks for the events in the order given by the total ordering. Second, for a post-node, one can construct a ∀FA on finite strings instead of a DFA, along the lines indicated in [AEN99]. This ∀FA runs several small DFA checks in parallel.…”

Section: Model Checking With Mtd'smentioning

confidence: 99%

“…The DFA's check (a) each waveform, (b) each sequential dependency, using the linear size DFA's for the location function, and (c) each concurrent dependency, by locating one event e of that dependency, and checking pairwise that for each other event f in the dependency, e and f occur at the same instant. As shown in [AEN99], these checks can be done with a ∀FA of size cubic in the RTD size. We can replace the DFA's for the post nodes in the semantics with these ∀FA's.…”

Section: Model Checking With Mtd'smentioning

confidence: 99%

“…In this paper, we present a complementary visual notation for specifying properties that are universal in nature; that is, properties that should hold for every computation of a system. This notation, called Modular Timing Diagrams (MTD's), is an extension of the Timing Diagrams (TD's) notation, that is widely used in the hardware industry to specify universal properties of hardware protocols [DJS94,Fis96,AEN99]. MTD's form the basis of our proposed framework for specifying and analyzing properties of asynchronous systems in a modular manner.…”

Section: Introductionmentioning

confidence: 99%

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Visual Specifications for Modular Reasoning about Asynchronous Systems

Amla

Namjoshi

Trefler

2002

Formal Techniques for Networked and Distributed Sytems — FORTE 2002

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Abstract. We propose a framework that closely ties together visual specification and modular reasoning of asynchronous systems. The basis of the framework is a new notation, called Modular Timing Diagrams (MTD's), for specifying the universal properties about causality and timing of events in an asynchronous system. MTD's are complementary in nature to Message Sequence Charts, that are typically used to specify existential properties. Our framework includes two algorithms for formal reasoning with MTD's. The first is an efficient polynomial-time model checking algorithm. The second is an algorithm for automatically generating an assume-guarantee partitioning of an MTD, that exploits its inherent decompositional structure. We show how to use this decomposition for modular reasoning with MTD properties in conjunction with an asynchronous compositional reasoning rule. To illustrate the notation and our method, we describe a case study where we specified telephony features, such as call forwarding with MTD's, and verified these properties on an asynchronous telephony model. The compositional reasoning methods led to savings of 15%-80% in verification times, and comparable savings in space.

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Temporal Modalities for Concisely Capturing Timing Diagrams

Chockler¹,

Fisler²

2005

Lecture Notes in Computer Science

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Abstract. Timing diagrams are useful for capturing temporal specifications in which all mentioned events are required to occur. We first show that translating timing diagrams with both partial orders on events and don't-care regions to LTL potentially yields exponentially larger formulas containing several non-localized terms corresponding to the same event. This raises a more fundamental question: which modalities allow a textual temporal logic to capture such diagrams using a single term for each event? We define the shapes of partial orders that are captured concisely by a hierarchy of textual linear temporal logics containing future and past time operators, as well Laroussinie et al's forgettable past operator and our own unforeseen future operator. Our results give insight into the temporal abstractions that underlie timing diagrams and suggest that the abstractions in LTL are significantly weaker than those captured by timing diagrams.

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Efficient Decompositional Model Checking for Regular Timing Diagrams

Cited by 14 publications

References 22 publications

Towards Diagrammability and Efficiency in Event Sequence Languages

Towards Diagrammability and Efficiency in Event Sequence Languages

Visual Specifications for Modular Reasoning about Asynchronous Systems

Temporal Modalities for Concisely Capturing Timing Diagrams

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