Temporal Modalities for Concisely Capturing Timing Diagrams

Abstract

Abstract. Timing diagrams are useful for capturing temporal specifications in which all mentioned events are required to occur. We first show that translating timing diagrams with both partial orders on events and don't-care regions to LTL potentially yields exponentially larger formulas containing several non-localized terms corresponding to the same event. This raises a more fundamental question: which modalities allow a textual temporal logic to capture such diagrams using a single term for each event? We define the shapes of partial orders that are captured concisely by a hierarchy of textual linear temporal logics containing future and past time operators, as well Laroussinie et al's forgettable past operator and our own unforeseen future operator. Our results give insight into the temporal abstractions that underlie timing diagrams and suggest that the abstractions in LTL are significantly weaker than those captured by timing diagrams.

Formalizing Timing Diagram Requirements in Discrete Duration Calculus

“…Example (Ordered Stack) Let us now consider the timing diagram in Fig. 4 adapted from [CF05]. Rise and fall of successive signals follow a stack discipline.…”

“…In general, presence of nominals distinguishes SeCeNL from logics like PSL-Sugar. In formalizing behaviour of hardware circuits it has been proposed that regular expressions are not enough and operators such as pipelining have been introduced [CF05]. These are a form of synchronization and they can be easily expressed using nominals too.…”

“…al. state that the less than satisfactory adoption of formal methods in timing diagram domain can be partly attributed to the gulf that exists between graphical timing diagrams and textual temporal logic -expressing various timing dependencies that can exist among signals that can be illustrated so naturally in timing diagrams is rather tedious in temporal logics [CF05]. As a result, hardware designers use timing diagrams informally without any well defined semantics which make them unamenable to automatic design verification techniques.…”

“…There have been numerous attempts at formalizing timing diagram constraints in the framework of temporal logics such as the timing diagram logic [Fis99], with LTL formulas [CF05], and as synchronous regular timing diagrams arXiv:1705.04510v1 [cs.LO] 12 May 2017…”