Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors

Eyerman, Stijn; Eeckhout, Lieven; Bosschere, Koen De

doi:10.1109/date.2006.243735

Cited by 52 publications

(33 citation statements)

References 12 publications

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“…The data gathered by offline learning experiments can then be used to predict the performance and power consumption of benchmark applications with reasonable accuracy. Eyerman et al [12], on the other hand, used a two-phase genetic local search algorithm to simulate out-of-order processors. The first stage applies statistical simulation to prune the design space, which is followed by the detailed simulation of a specific region of interest to reduce the simulation time.…”

Section: Related Workmentioning

confidence: 99%

Towards Architectural Design Space Exploration for Heterogeneous Manycores

Xypolitidis

Shabani

Khandeparkar

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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Abstract-Today many of the high performance embedded processors already contain multiple processor cores and we see heterogeneous manycore architectures being proposed. Therefore it is very desirable to have a fast way to explore various heterogeneous architectures through the use of an architectural design space exploration tool, giving the designer the option to explore design alternatives before the physical implementation.In this paper, we have extended Heracles, a design space exploration tool for (homogeneous) manycore architectures, to incorporate different types of processing cores, and thus allow us to model heterogeneity. Our tool, called the Heterogeneous Heracles System (HHS), can besides the already supported MIPS core also include OpenRISC cores. The new tool retains the possibility available in Heracles to perform register transfer level (RTL) simulations of each explored architecture in Verilog as well as synthesizing it to field-programmable gate arrays (FPGAs). To facilitate the exploration of heterogeneous architectures, we have also extended the graphical user interface (GUI) to support heterogeneity. This GUI provides options to configure the types of core, core settings, memory system and network topology.Some initial results on FPGA utilization are presented from synthesizing both homogeneous and heterogeneous manycore architectures, as well as some benchmark results from both simulated and synthesized architectures.

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Section: Related Workmentioning

confidence: 99%

Towards Architectural Design Space Exploration for Heterogeneous Manycores

Xypolitidis

Shabani

Khandeparkar

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

View full text Add to dashboard Cite

show abstract

“…Yi et al [17] use a PlackettBurman design of experiment to identify the important axes in the design space in order to drive the design process. Eyerman et al [4] leverage machine learning techniques to more quickly steer the search process to the optimum design point. Lee and Brooks [13] use empirical models to explore the design space of adaptive microarchitectures, while Karkhanis and Smith [10] use mechanistic model to guide the design of application-specific out-of-order processors.…”

Section: B Design Space Explorationmentioning

confidence: 99%

How sensitive is processor customization to the workload's input datasets?

Breughe

Chen

et al. 2011

2011 IEEE 9th Symposium on Application Specific Processors (SASP)

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Abstract-Hardware customization is an effective approach for meeting application performance requirements while achieving high levels of energy efficiency. Application-specific processors achieve high performance at low energy by tailoring their designs towards a specific workload, i.e., an application or application domain of interest. A fundamental question that has remained unanswered so far though is to what extent processor customization is sensitive to the training workload's input datasets. Current practice is to consider a single or only a few input datasets per workload during the processor design cycle -the reason being that simulation is prohibitively time-consuming which excludes considering a large number of datasets. This paper addresses this fundamental question, for the first time. In order to perform the large number of runs required to address this question in a reasonable amount of time, we first propose a mechanistic analytical model, built from first principles, that is accurate within 3.6% on average across a broad design space. The analytical model is at least 4 orders of magnitude faster than detailed cycle-accurate simulation for design space exploration. Using the model, we are able to study the sensitivity of a workload's input dataset on the optimum customized processor architecture. Considering MiBench benchmarks and 1000 datasets per benchmark, we conclude that processor customization is largely dataset-insensitive. This has an important implication in practice: a single or only a few datasets are sufficient for determining the optimum processor architecture when designing application-specific processors.

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“…DSE techniques thus either do not support these systems or have to restrict precise performance estimation to a small subset of the design space [17].…”

Section: Introductionmentioning

confidence: 99%

Fast and Precise Cache Performance Estimation for Out-Of-Order Execution

Douma

Altmeyer

Pimentel

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Design space exploration (DSE) is a key ingredient of system-level design, enabling designers to quickly prune the set of possible designs and determine, e.g., the number of the processing cores, the mapping of application tasks to cores, and the core configuration such as the cache organization. High-level performance estimation is a principle component of any systemlevel DSE: it has to be fast and sufficiently precise. Modern out-oforder architectures with caches pose a significant problem to this performance estimation process, as no simple one-to-one mapping of the number of cache misses and resulting cycle time exists. We present a high-level cache performance-estimation framework for out-of-order processors. Evaluation shows that our prediction method is on average 15 times faster than cycleaccurate simulation, while our estimates only show an average error of below 3.5%, reduce the pessimism of a naive highlevel performance estimation by around 66%, and still maintain a high fidelity. Our approach thus enables quick yet accurate performance estimation and extends the applicability of systemlevel DSE to out-of-order processors with caches.

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Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors

Cited by 52 publications

References 12 publications

Towards Architectural Design Space Exploration for Heterogeneous Manycores

Towards Architectural Design Space Exploration for Heterogeneous Manycores

How sensitive is processor customization to the workload's input datasets?

Fast and Precise Cache Performance Estimation for Out-Of-Order Execution

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