Efficient embedded architectures for fast-charge model predictive controller for battery cell management in electric vehicles

Madsen, Anne K.; Perera, Darshika G.

doi:10.1186/s13639-018-0084-3

Cited by 13 publications

(14 citation statements)

References 26 publications

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“…Advantages of bi-directional multi-ported memories over uni-directional ones are detailed with several examples in Section IV.D. Furthermore, from our previous work, it was observed that utilizing bi-directional multiported memories (compared to the uni-directional ones) can dramatically increase the speed-performance of certain embedded applications such as model predictive control applications [12], [13] and data mining/analytics applications [36], [37].…”

Section: A Our Novel Bi-directional Multi-ported Memory Architecturesmentioning

confidence: 99%

“…Furthermore, with bi-directional multiported memories, the designers have the flexibility to change the number of read and write transactions as needed on-thefly at any time. Also, from our previous work [12], [13], it was observed that certain control systems applications, such as Model Predictive Control, executed on FPGAs, can be dramatically accelerated using bi-directional port multiported memories.…”

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Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

2020

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With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multiported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time. Previously, we introduced unique and efficient uni-directional multi-ported memories, which were created in such a way to significantly reduce the design and routing complexity. In this research work, we introduce novel, unique, and efficient bidirectional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency. To the best of our knowledge, no similar work exists in the literature that provide multi-ported memory designs without the circular paths. Experiments are performed to evaluate the feasibility and efficiency of our bidirectional multi-ported memory designs. These results and analyses illustrate that our bi-directional multiported memories are far more efficient compared to the existing ones in the literature. Due to lower design and routing complexity compared to the existing ones, our simplified memories would enable seamless integration to the next-generation FPGAs with minimal design cost. INDEX TERMS Bi-directional ports, FPGAs, embedded memory, embedded systems, multi-ported memory, on-chip BRAMs.

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Section: A Our Novel Bi-directional Multi-ported Memory Architecturesmentioning

confidence: 99%

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confidence: 99%

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

2020

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“…This has led to research in techniques for battery management systems (BMS), including techniques to optimize the control of the battery cells using Model Predictive Control (MPC) to enhance performance, while extending the useful life of the battery cells as well as providing safe operating environment [4], [5], [6]. MPC is one of the most effective techniques for cell-level monitoring and controlling of the battery packs [7], [8], since it inherently incorporates constraints and refines the safety margins, thus enabling the battery cells to be fully utilized. However, MPC is computationally intensive and typically used for industrial control.…”

Section: Introductionmentioning

confidence: 99%

Toward Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based Model Predictive Control Smart Sensor for HEV Battery Cell Management

Madsen,

Perera

2023

IEEE Access

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In the era of climate change, and with the rapid depletion of fossil resources, efficient and sustainable transportation systems, such as hybrid electric vehicles (HEVs), are becoming imperative. The cornerstone of HEVs is the efficient battery technology, in order to extend the useful life of the battery and to provide improved performance to fossil fuel technology. Model predictive control (MPC) is an effective technique for battery management systems (BMS), which enables cell-level monitoring and controlling of the battery pack, reducing the safety margin of operation, while maintaining the safety requirements. Furthermore, utilizing the physics-based model (PBM) of the battery allows the control system to operate on the chemical and physical process of the battery that are the root cause of battery degradation. The non-linear extended Kalman filter (EKF) serves as the state observer to monitor the physical and chemical properties/processes of each battery cell, since these are internal processes of the battery, making them physically unobservable. The amalgamation of the aforementioned techniques, i.e., MPC, PBM, and EKF, can extend the useful life of the battery cell/pack, especially for lithium-ion batteries. In real-world scenarios, HEVs and smart applications often require portable BMS, compelling BMS to be executed on highly constrained embedded devices. Also, the inherent adaptive control process of physics-based (PB) MPC is uniquely suited for smart systems/applications. However, the high computational complexity of PB-MPC, comprising PB-EKF, prevents it from being realized on resource-constrained embedded devices, making it infeasible for portable BMS. In this research work, we introduce novel, unique, and efficient FPGA-based embedded hardware accelerator for PB-MPC smart sensor (comprising PB-EKF) for BMS, specifically on embedded devices, by addressing the computational complexity of PBM. Our proposed embedded PB-MPC hardware accelerator achieved 58 times speedup compared to its embedded software counterpart, while maintain a small footprint required for portable systems. This speedup enables us to manage more battery cells utilizing a single chip compared to that of embedded processor-based solutions.

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“…In this regard, Field Programmable Gate Array (FPGA)-based hardware is one of the most promising avenues to deliver machine learning applications on highly constrained embedded platforms [10], not only because FPGAs provide a higher level of flexibility than ASICs (application-specific-integrated-circuits) and higher performance than software running on a processor, but also due to their many attractive traits including post-fabrication reprogrammability, dynamic partial reconfiguration capabilities, and reduced time-to-market. Our previous work demonstrated that FPGA's aforementioned traits indeed facilitate the support and acceleration of many real-time compute/data-intensive applications (not only machine learning [2,11,12], but also data mining [13,14], control systems [15,16], and security [17,18]), especially on resource-constrained embedded devices.…”

Section: Introductionmentioning

confidence: 99%

An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms

Ramadurgam

Perera

2021

Electronics

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Machine learning is becoming the cornerstones of smart and autonomous systems. Machine learning algorithms can be categorized into supervised learning (classification) and unsupervised learning (clustering). Among many classification algorithms, the Support Vector Machine (SVM) classifier is one of the most commonly used machine learning algorithms. By incorporating convex optimization techniques into the SVM classifier, we can further enhance the accuracy and classification process of the SVM by finding the optimal solution. Many machine learning algorithms, including SVM classification, are compute-intensive and data-intensive, requiring significant processing power. Furthermore, many machine learning algorithms have found their way into portable and embedded devices, which have stringent requirements. In this research work, we introduce a novel, unique, and efficient Field Programmable Gate Array (FPGA)-based hardware accelerator for a convex optimization-based SVM classifier for embedded platforms, considering the constraints associated with these platforms and the requirements of the applications running on these devices. We incorporate suitable mathematical kernels and decomposition methods to systematically solve the convex optimization for machine learning applications with a large volume of data. Our proposed architectures are generic, parameterized, and scalable; hence, without changing internal architectures, our designs can be used to process different datasets with varying sizes, can be executed on different platforms, and can be utilized for various machine learning applications. We also introduce system-level architectures and techniques to facilitate real-time processing. Experiments are performed using two different benchmark datasets to evaluate the feasibility and efficiency of our hardware architecture, in terms of timing, speedup, area, and accuracy. Our embedded hardware design achieves up to 79 times speedup compared to its embedded software counterpart, and can also achieve up to 100% classification accuracy.

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Efficient embedded architectures for fast-charge model predictive controller for battery cell management in electric vehicles

Cited by 13 publications

References 26 publications

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

Toward Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based Model Predictive Control Smart Sensor for HEV Battery Cell Management

An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms

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