Efficient fault simulation on many-core processors

Kochte, Michael A.; Schaal, Marcel; Wunderlich, Hans-Joachim; Zoellin, Christian G.

doi:10.1145/1837274.1837369

Cited by 49 publications

(19 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Each gate containing the faults was encoded using a 32-bit word, while also storing the input port numbers for identifying the location of the faults. Koshte et al [11] proposed a Parallel Pattern Single Fault Propagation algorithm on the GPU where they encoded the different gate and fault data over the computer's word. They limited the number of inputs of every logic gate to two input ports, so they can constrain the memory size of the circuit and fault data.…”

Section: Related Workmentioning

confidence: 99%

Mu-GSIM: A mutation testing simulator on GPUs

Tong

Boulé

Žilić

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

View full text Add to dashboard Cite

Graphics Processing Units (GPUs) have recently gained widespread usage as an advanced parallel platform for accelerating compute intensive applications. The maturity of programming interfaces and the improved programmability of GPUs have enabled the development of parallel algorithms that leverage the wealth of compute power provided by them. In this paper, we present µ-GSIM, a GPU-based simulation tool that leverages the inherent bit parallelism of GPUs for accelerating simulations of mutated digital circuits. We propose an efficient mapping of multiple mutated circuits on the GPU's device memory, where we exploit as much data parallelism as possible so our GPU simulation kernel can achieve maximal performance by operating on independent data. Results show that with the largest ITC'99 circuit benchmarks we were able to achieve a 60% decrease in memory usage while gaining a 5.4× increase in simulation performance. Additionally, we demonstrated a speedup of at least 95× against a commercial event-driven simulation tool running on a conventional processor. This is beneficial in the quest for improving test quality.

show abstract

Section: Related Workmentioning

confidence: 99%

Mu-GSIM: A mutation testing simulator on GPUs

Tong

Boulé

Žilić

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

View full text Add to dashboard Cite

show abstract

“…During the gate-level fault simulation a large degree of parallelism can be exploited by efficient evaluation of faults, patterns and gates in parallel [28]. Here, the concurrent fault simulation algorithm [29] is used to achieve high efficiency by simulating several faults in parallel such that gains are obtained by common sensitization criteria amongst faults.…”

Section: Wrapper For Gate-level Modelsmentioning

confidence: 99%

Efficient multi-level fault simulation of HW/SW systems for structural faults

Baranowski

Carlo

Hatami

et al. 2011

Sci. China Inf. Sci.

Self Cite

View full text Add to dashboard Cite

In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate-and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate-and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average. CitationBaranowski R, Di Carlo S, Hatami N, et al. Efficient multi-level fault simulation of HW/SW systems for structural faults.

show abstract

“…One of the trends is the development of such methods for multicore systems with shared-memory [9]. Obviously, the performance of the same method to the different parallel systems varies greatly.…”

Section: Introductionmentioning

confidence: 99%

Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping

Ivanov¹

2016

IJMO

View full text Add to dashboard Cite

Abstract-A new algorithm for parallel fault simulation of VLSI on multicore workstations with common memory is proposed. To speeding up the algorithm two-level parallelization is used. First, main schema of the algorithm is based on the concurrent many-threaded simulation of the groups of faults for each input vector. Second, each group of faults is simulated in bit-parallel way. The dynamic fault grouping is adopted. The results of computational experiments on ISCAS-89 benchmarks circuits are reported, which are obtained on the 12-core workstation.

show abstract

Efficient fault simulation on many-core processors

Cited by 49 publications

References 21 publications

Mu-GSIM: A mutation testing simulator on GPUs

Mu-GSIM: A mutation testing simulator on GPUs

Efficient multi-level fault simulation of HW/SW systems for structural faults

Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping

Contact Info

Product

Resources

About