Efficient field processing cores in an innovative protocol processor system-on-chip

Lykakis, G.; Mouratidis, Nikos; Vlachos, K.; Nikolaou, Nikos; Perissakis, Stylianos; Sourdis, G.; Konstantoulakis, G.; Pnevmatikatos, D.; Reisis, D.

doi:10.1109/date.2003.1253798

Cited by 3 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Using our architecture, we can guarantee a constant throughput independent of the data manipulations that are performed. In other architectures, like the RISC-based FMO in [9], throughput is affected by the sequence of operations. We enable a true hardware performance, while still adhering programmability.…”

Section: Architecture and Implementationmentioning

confidence: 99%

“…While a Field Extraction Engine extracts important header fields, a Field Modification Unit (FMO) accomplishes modifications based on the fields received from the Protocol Processing Engine. The FMO is a small custom RISC with a three-stage pipeline and fully programmable by firmware [9]. In ASIC technology a maximum throughput of 6.4 Gbps (32 Bit @ 200 MHz) can be reached.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors

Meitinger

Ohlendorf

Wild

et al. 2007

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

View full text Add to dashboard Cite

In this paper we introduce a programmable stream processing engine working as a co-processor in a Network Processor egress path. By using a special pipelining architecture several generic manipulations can be performed on-the-fly on a packet data stream with line-speed. In two measurement scenarios for IP forwarding and IP tunneling we demonstrate the benefits of the Post-Processor concept compared to a pure software reference implementation.

show abstract

Section: Architecture and Implementationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors

Meitinger

Ohlendorf

Wild

et al. 2007

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

View full text Add to dashboard Cite

show abstract

Software processing performance in network processors

Papaefstathiou¹,

Kornaros²,

Zervos³

Proceedings Design, Automation and Test in Europe Conference and Exhibition

View full text Add to dashboard Cite

To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, an alternative to the ASICs that traditionally were used to implement packet-processing functions in hardware, called network processors (NPs), has emerged. In this paper, we briefly outline the architecture of such an innovative network processor aiming at the acceleration of protocol processing in high-speed network interfaces, and we use this architecture as a case study for our measurements. We focus on the performance of the general purpose processors used for executing high level protocol processing, since this part proves to be the bottleneck of the design. The performance is analyzed by executing a set of widely used, real applications and by applying network traffic according to certain stochastic criteria. The performance of the RISC used is compared with that of other well-known CPU architectures so as to verify that our results are applicable to the general network processors era. As our results demonstrate, the bottleneck of the majority of the network processors is the general-purpose processing units used, since today's network protocols need a great amount of high-level processing. On the other hand the specific purpose processors or co-processors, optimized for certain part of the network packet processing, involved in such systems, can provide the power needed, even at today's ultra high network speeds.

show abstract

A hardware multi-threading architecture for protocol processors

Qin

Wang

et al. 2010

2010 IEEE 12th International Conference on Communication Technology

View full text Add to dashboard Cite

Efficient field processing cores in an innovative protocol processor system-on-chip

Cited by 3 publications

References 7 publications

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors

Software processing performance in network processors

A hardware multi-threading architecture for protocol processors

Contact Info

Product

Resources

About