Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array

Rahman, Atul; Lee, Jong-Eun; Choi, Ki‐Young

doi:10.3850/9783981537079_0833

Cited by 50 publications

(30 citation statements)

References 7 publications

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“…weight buf f er ≥ T kx×T ky×T if ×T of ×bit width (10) weight buf f er ≥ peak weight memory demand (11) Similarly, the constraints on the activation buffer size are:…”

Section: Multidimensional Optimizationmentioning

confidence: 99%

“…Hence, even though new DNN models are evolving rapidly and differ in their network architectures significantly, ASIC-and FPGA-based accelerators are still capable of processing various DNNs efficiently. FPGA-based accelerators [5], [6], [7], [8], [9], [10], [11], [12], [13] provide high parallelism and fast time-to-market. For example, an embedded FPGA platform is used as a convolver with dynamic-precision data quantization in [6] to achieve high throughput.…”

Section: Introductionmentioning

confidence: 99%

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Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Che

et al. 2021

IEEE Trans. Comput.

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Deep neural networks (DNNs) have been shown to outperform conventional machine learning algorithms across a wide range of applications, e.g., image recognition, object detection, robotics, and natural language processing. However, the high computational complexity of DNNs often necessitates extremely fast and efficient hardware. The problem gets worse as the size of neural networks grows exponentially. As a result, customized hardware accelerators have been developed to accelerate DNN processing without sacrificing model accuracy. However, previous accelerator design studies have not fully considered the characteristics of the target applications, which may lead to sub-optimal architecture designs. On the other hand, new DNN models have been developed for better accuracy, but their compatibility with the underlying hardware accelerator is often overlooked. In this article, we propose an application-driven framework for architectural design space exploration of DNN accelerators. This framework is based on a hardware analytical model of individual DNN operations. It models the accelerator design task as a multi-dimensional optimization problem. We demonstrate that it can be efficaciously used in application-driven accelerator architecture design: we use the framework to optimize the accelerator configurations for eight representative DNNs and select the configuration with the highest geometric mean performance. The geometric mean performance improvement of the selected DNN configuration relative to the architectural configuration optimized only for each individual DNN ranges from 12.0% to 117.9%. Given a target DNN, the framework can generate efficient accelerator design solutions with optimized performance and area. Furthermore, we explore the opportunity to use the framework for accelerator configuration optimization under simultaneous diverse DNN applications. The framework is also capable of improving neural network models to best fit the underlying hardware resources. We demonstrate that it can be used to analyze the relationship between the operations of the target DNNs and the corresponding accelerator configurations, based on which the DNNs can be tuned for better processing efficiency on the given accelerator without sacrificing accuracy.

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“…weight buf f er ≥ T kx×T ky×T if ×T of ×bit width (10) weight buf f er ≥ peak weight memory demand (11) Similarly, the constraints on the activation buffer size are:…”

Section: Multidimensional Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Che

et al. 2021

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…These works typically use a set of RTL modules combined with a design space exploration tool to find the optimal architectural parameters. Rahman et al [20] propose a scalable array-based CNN accelerator with heavy input reuse. Motamedi [17] uses a roofline model for performance to guide hardware generation.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

Zhao

Song

Zhang³

et al. 2017

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

342

146

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Convolutional neural networks (CNN) are the current stateof-the-art for many computer vision tasks. CNNs outperform older methods in accuracy, but require vast amounts of computation and memory. As a result, existing CNN applications are typically run on clusters of CPUs or GPUs. Research on FPGA acceleration of CNN workloads has achieved reductions in power and energy consumption. However, large GPUs outperform modern FPGAs in throughput, and the existence of compatible deep learning frameworks give GPUs a significant advantage in programmability. Recent work in machine learning demonstrates the potential of very low precision CNNs-i.e., CNNs with binarized weights and activations. Such binarized neural networks (BNNs) appear well suited for FPGA implementation, as their dominant computations are bitwise logic operations and their memory requirements are greatly reduced. A combination of low-precision networks and high-level design methodology may help address the performance and productivity gap between FPGAs and GPUs. In this paper, we present the design of a BNN accelerator that is synthesized from C++ to FPGA-targeted Verilog. The accelerator outperforms existing FPGA-based CNN accelerators in GOPS as well as energy and resource efficiency.

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“…Recently, in order to realize neural system models, reconfigurable digital platforms have been utilized [15]- [22]. Critical challenges of the digital implementation include Through FPGA it is possible to achieve lower power consumption [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

Digital Implementation of a Spiking Convolutional Neural Network for Tumor Detection

Karimi

2020

Informacije MIDEM

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The structural variation of the brain tissue creates challenges for detection of tumors in MRI images. In this paper, an architecture for spiking convolutional neural networks (SCNNs) is implemented in an embedded system and their potential is evaluated in terms of hardware utilization and power consumption in complex applications such as tumor detection. Accordingly, the structure of the proposed SCNN is implemented on a field-programmable gate array (FPGA) using fixed point arithmetic. To evaluate the speed, accuracy and flexibility of the proposed SCNN, Izhikevich neuron model is used with the spike-timing-dependent plasticity (STDP) learning rule. The suggested neural network is explored for digital implementation possibility and costs. Results of the hardware synthesis and digital implementation are presented on an FPGA. Digitalna implementacija sunkovnih nevronskih mrež za detekcijo tumorjevIzvleček: Strukturne razlike v možganskem tkivu predstavljajo iziv pri detekciji tumorjev v MRI slikah. Članek opisuje arhitekturo implementacije sunkovnih konvolucijskih nevronskih mrež v vgradnih sistemih. Njihov potencial je ocenjen na osnovi strojne uporabnosti in porabe pri detekciji tumorjev. Struktura je implementirana v FPGA okolju. Ocena hitrosti, natančnosti in fleksibilnosti je opravljena z Izhikevichevim nevronskim modelom. Ključne

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Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array

Cited by 50 publications

References 7 publications

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

Digital Implementation of a Spiking Convolutional Neural Network for Tumor Detection

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