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This paper shows a new methodology to design the hardware for computing square root of N-bit unsigned numbers. The proposed hardware design is based on the modified nonrestoring square root algorithm. Two different hardware designs, sequential pipeline architecture and asynchronous architecture for computing N-bit fixed point square root operation are proposed. The synthesis report of the designed FPGA based pipelined hardware for 32-bit square root operation shows that the usage of the logical resources of FPGA is significantly less than that of the earlier proposed pipelined hardware designs based on modified non-restoring algorithm. Moreover, the proposed pipelined hardware design can be configured to calculate square root of 32-bit number in 16 and 8 clock cycles. The maximum frequency achieved for the operation latency of 16-clock cycles for computing 32-bit unsigned square root is 403.770 MHz. The maximum frequency achieved for operating latency of 8-clock cycles is 260.233 MHz. On the other side, proposed asynchronous architecture based FPGA hardware design supersedes the earlier proposed asynchronous hardware designs for N-bit square root operation in terms of the less usage of hardware resources. Both the pipelined and asynchronous hardware designs are tested on Xilinx Virtex 7 XC7VX980T-2, Virtex 5 XC5VLX330T-2 and Spartan 3E XC3S1600E-5 FPGAs.

IEEE 754 standard double precision (64-bit) binary floating point arithmetic unit is often necessary in complex digital signal processing applications. The basic operations, floating point addition and subtraction, need to be optimized to efficiently compute floating point multiplier, divider and square root. However, the main challenge is to design the floating point arithmetic unit hardware that uses fewer logical resources of FPGA and ASIC and has a maximum operating frequency with a fewer number of clock cycles. This paper proposes a new, efficient hardware design methodology for implementing double precision floating point addition and subtraction. The pipeline hardware design is implemented on Virtex-6 and Virtex-5 Xilinx FPGA. As per the synthesis result, the maximum operating frequency achieved for the proposed hardware design for clock latency of 8 cycles is significantly higher than the previous hardware designs. Furthermore, area overhead is 50 percent fewer than that of the earlier proposed hardware designs for computing IEEE 754 compliant double precision floating point addition and subtraction.

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