Efficient generation of test patterns using Boolean difference

Larrabee, T.

doi:10.1109/test.1989.82368

Cited by 86 publications

(63 citation statements)

References 8 publications

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“…There are also algorithms basing the search on the function of the circuit, i.e. independently from the topological information; this is the case of boolean differences-based approaches, as described in [32].…”

Section: Automatic Test Pattern Generation (Atpg)mentioning

confidence: 99%

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Mele

Favalli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Automatic Test Pattern Generation (Atpg)mentioning

confidence: 99%

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Mele

Favalli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…[27], [43]. CNF-based ATPG methods can exploit many basic concepts of the netlist-based approaches, and vice versa.…”

Section: F) Decision Tree (Backtracking)mentioning

confidence: 99%

“…CNF-based ATPG methods can exploit many basic concepts of the netlist-based approaches, and vice versa. As pointed out before, controllability is a SAT problem by nature and observability can be mapped to SAT using the notion of Boolean difference [27]. Constraints like unique sensitization conditions can be expressed in terms of clauses that are added to the CNF.…”

Section: F) Decision Tree (Backtracking)mentioning

confidence: 99%

Sat and ATPG: Algorithms for Boolean Decision Problems

Kunz

Marques-Silva

Malik

2002

Logic Synthesis and Verification

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“…Satisability-based algorithms [5,12,21] translate the test generation problem into a formula in conjunctive normal form (CNF) [7]. A branch-and-bound strategy is then used to nd a satisfying assignment, which corresponds to a test for the target fault.…”

Section: Introductionmentioning

confidence: 99%

A satisfiability-based test generator for path delay faults in combinational circuits

Chen

Gupta

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

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This paper describes a new formulation to generate robust tests for path delay faults in combinational circuits based o n B o olean satisability. Conditions to detect a target path delay fault are r epresented b y a Boolean formula. Unlike the technique described in [16], which extracts the formula for each path delay fault, the proposed formulation needs to extract the formula only once for each circuit cone. Experimental results show tremendous time saving on formula extraction compared to other satisability-based A TPG algorithms. This also leads to low test generation time, especially for circuits that have many paths but few outputs. The proposed formulation has also been modied to generate other types of tests for path delay faults.

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Efficient generation of test patterns using Boolean difference

Cited by 86 publications

References 8 publications

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Sat and ATPG: Algorithms for Boolean Decision Problems

A satisfiability-based test generator for path delay faults in combinational circuits

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