Efficient Identification of Wafer Edge’s Defect with Volume Diagnosis Analysis and Plasma-FIB Planar Deprocessing

Abstract

In the failure analysis (FA) of modern semiconductor logic device manufactured in foundry fab, efficient identification of wafer edge’s defect was studied by using volume diagnosis analysis and plasma-focused ion beam (FIB) planar deprocessing. As the chip from wafer edge has multiple defective locations, there is the limitation of the conventional FA work to identify them. Here, we used volume diagnosis analysis to identify the multiple defective locations within chip and plasma-FIB planar deprocessing to delayer those locations and find out defects. The actual FA work verified that new workflow successfully identified the different defects from different layers from the chip of wafer edge and efficiently accelerated the quantity of FA results, importantly leading to more representative status of inline defect.

Chip Recombination Method in Planar Deprocessing – A Solution for Failure Analysis on Chip Edge Defects

“…A healthy manufacturing line is the key to success and to ensure all above goals are achieved. FA plays an important role in manufacturing process decisions when holding, releasing or scrapping wafers [3]. It is important for FA to accurately identify yield detractor on a timely basis for wafers impacted by low yield and quality issue.…”