No abstract

In the failure analysis (FA) of modern semiconductor logic device manufactured in foundry fab, efficient identification of wafer edge’s defect was studied by using volume diagnosis analysis and plasma-focused ion beam (FIB) planar deprocessing. As the chip from wafer edge has multiple defective locations, there is the limitation of the conventional FA work to identify them. Here, we used volume diagnosis analysis to identify the multiple defective locations within chip and plasma-FIB planar deprocessing to delayer those locations and find out defects. The actual FA work verified that new workflow successfully identified the different defects from different layers from the chip of wafer edge and efficiently accelerated the quantity of FA results, importantly leading to more representative status of inline defect.

No abstract

Efficient and effective failure analysis (FA) of low-resistive defect was studied by using layout-aware and volume diagnosis. Small or marginal defect is one of the most difficult defectivities to identify during FA effort, especially if defect-induced resistance is not as high as the electrical isolation can detect. Here, we used new analysis methodologies, particularly using layout-aware and volume diagnosis, and prioritizing patterns in terms of a defective risk for following FA. The actual FA work verified that new analysis methodologies successfully identified low-resistive defect of Back-End-of-Line (BEOL) which was not detected by a conventional way and efficiently reduced the turn-around time (TAT) of physical failure analysis (PFA) by 57%, prompting fast feedback to fab.