Efficient implementation of HEVC decoder on Zynq SoC platform

Ayadi, Lella Aicha; Loukil, Hassen; Ayed, Mohamed Ali Ben; Nouri, Mohammad

doi:10.1109/atsip.2018.8364342

Cited by 4 publications

(3 citation statements)

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“…From Table 7, we can conclude that our design has better performance than those in [27][28][29]. On the other hand, our design allows a high decrease in power consumption equal to 99% with almost the same performance compared to [30].…”

Section: Iq/it Streammentioning

confidence: 79%

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An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16 , and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

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Section: Iq/it Streammentioning

confidence: 79%

“…1.2 GHz [29] 1080 p at 0.25 1.609 Watt HEVC ARM Cortex-A9 (INTER) processor at 700 MHz + interpolation filter accelerator at 100 MHz [30] 1080 p at 9.…”

Section: Ref Fpsmentioning

confidence: 99%

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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show abstract

“…In [11,12], Ayadi et al proposed an FPGA-accelerated HEVC decoder on a Zynq SoC platform. Based on the decoding time distribution of the reference decoder running on an ARM processor, the authors determined the calculation of interpolation ilters during motion compensation to be the most computationally expensive part and implemented this function on the FPGA part of the Zynq board.…”

Section: Inter-frame Compressionmentioning

confidence: 99%

Image and Video Coding Techniques for Ultra-low Latency

et al. 2022

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The next generation of wireless networks fosters the adoption of latency-critical applications such as XR, connected industry, or autonomous driving. This survey gathers implementation aspects of different image and video coding schemes and discusses their tradeoffs. Standardized video coding technologies such as HEVC or VVC provide a high compression ratio, but their enormous complexity sets the scene for alternative approaches like still image, mezzanine, or texture compression in scenarios with tight resource or latency constraints. Regardless of the coding scheme, we found inter-device memory transfers and the lack of sub-frame coding as limitations of current full-system and software-programmable implementations.

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