Efficient Intra Prediction Mode Decision for H.264 Video

Chun, Seong Soo; Yoon, Ja-Cheon; Sull, Sanghoon

doi:10.1007/11581772_15

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…Different works have been proposed [9][10][11][12][13]. For our architecture, the MB pixels are loaded into a dual RAM (Random Access Memory) for reordering and then give (to the residual or reconstruction blocks) by sets of 16 pixels (4 × 4 block).…”

Section: Intra 16 × 16 Predictionmentioning

confidence: 99%

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Loukil¹,

Werda²,

Nouri³

et al. 2010

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In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

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Section: Intra 16 × 16 Predictionmentioning

confidence: 99%

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Loukil¹,

Werda²,

Nouri³

et al. 2010

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“…As it is shown in the top-level block diagram of an H.264 encoder in Figure 1, the INTRA 4X4 is composed by intra prediction 4x4, transform 4x4, quantization 4x4, inverse quantization and inverse transform [1][2][3]. Among them, several researchers have focused on INTRA 4X4 processing that includes computationally expensive operations such as intra prediction and integer transformation [4][5][6][7][8][9][10]. A number of recent papers have been published for the fast execution of intra prediction of 4x4 Luma blocks that requires the most computation for intra frame processing.…”

Section: Introductionmentioning

confidence: 99%

An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

Loukil¹,

Kaanich²,

Nouri³

et al. 2008

2008 3rd International Design and Test Workshop

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In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4X4 is composed by intra prediction 4x4, integer transform 4x4, quantization 4x4, inverse integer transform 4x4, inverse quantization 4x4 .This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles. I.978-1-4244-3477-0/08/$25.00 ©2008 IEEE

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