Efficient modeling of static self-heating and thermal-coupling in multi-finger SiGe HBTs

Balanethiram, Suresh; Chakravorty, Anjan; D'Esposito, Rosario; Fregonèse, Sébastien; Zimmer, Thomas

doi:10.1109/bctm.2015.7340557

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…The related design considerations will be given in the following based on a general, analytical electro-thermal model of a transistor array. This novel model is neither limited to two elements with identical thermal properties [10], nor does it require electrical simulations like e.g., in [11], [12].…”

Section: Current Hogging Prevention Conceptmentioning

confidence: 99%

Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a <inline-formula> <tex-math notation="LaTeX">$5\times \text {6 V}_{\mathrm {pp}}$ </tex-math> </inline-formula> Chip-to-Chip Bondwire Output to an MZM PIC

Hettrich

Möller

2016

IEEE J. Solid-State Circuits

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This paper presents the design of a 5-channel driver array IC with a high total output current of 5×120 mA and a 6 V pp differential output voltage in SiGe bipolar technology. Special attention is given to design considerations for stable electrical and thermal operation and to the minimization of crosscoupling between the array channels. The related driver array is intended to realize a low-cost, small footprint 10×11.3 Gbit/s dense wavelength division multiplexing transmitter assembly, consisting of a pair of two driver ICs with a chip-to-chip bondwire interface to a ten-channel Mach-Zehnder modulator (MZM) in a photonic integrated circuit (PIC). The driver IC contains all required components, including the far-end terminations of the MZMs as well as an energy-efficient concept for flexible MZM biasing. Current hogging in the transistors of the output stages is mitigated by a novel circuit concept that is introduced along with an electro-thermal model for dense multi-transistor arrangements, especially in driver output stages. The performance of the design is demonstrated by measurement results of the driver array IC in both standalone and integrated PIC assemblies.

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Section: Current Hogging Prevention Conceptmentioning

confidence: 99%

Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a <inline-formula> <tex-math notation="LaTeX">$5\times \text {6 V}_{\mathrm {pp}}$ </tex-math> </inline-formula> Chip-to-Chip Bondwire Output to an MZM PIC

Hettrich

Möller

2016

IEEE J. Solid-State Circuits

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“…A state-of-theart static thermal model to cater the self-heating as well as thermal coupling effects in an n-finger transistor requires n 2 number of nodes as reported in [2]. Besides, modeling thermal coupling using voltage controlled-voltage-sources (VCVS) in series with the self-heating resistances degrades the speed performance of a thermal network as illustrated in [3].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Thermal Model for Multifinger SiGe HBTs Under Real Operating Condition

Nidhin

Pande

Yadav³

et al. 2020

IEEE Trans. Electron Devices

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In this work, we present a simple analytical model for electrothermal heating in multifinger bipolar transistors under realistic operating condition where all fingers are heating simultaneously. The proposed model intuitively incorporates the effect of thermal coupling among the neighboring fingers in the framework of self-heating bringing down the overall model complexity. Compared to the traditional thermal modeling approach for an n-finger transistor where the number of circuit nodes increases as n 2 , our model requires only n-number of nodes. The proposed model is scalable for any number of fingers and with different emitter geometries. The model is validated with 3D thermal simulations and measured data from STMicroelectronics B4T technology. The Verilog-A implemented model simulates 40% faster than the conventional model in a transient simulation of a five-finger transistor.

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Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs

hAnnaidh

Coyne

Lane

2017

2017 International Conference of Microelectronic Test Structures (ICMTS)

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Efficient modeling of static self-heating and thermal-coupling in multi-finger SiGe HBTs

Cited by 5 publications

References 10 publications

Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a <inline-formula> <tex-math notation="LaTeX">$5\times \text {6 V}_{\mathrm {pp}}$ </tex-math> </inline-formula> Chip-to-Chip Bondwire Output to an MZM PIC

Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a <inline-formula> <tex-math notation="LaTeX">$5\times \text {6 V}_{\mathrm {pp}}$ </tex-math> </inline-formula> Chip-to-Chip Bondwire Output to an MZM PIC

An Efficient Thermal Model for Multifinger SiGe HBTs Under Real Operating Condition

Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs

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