Efficient Multi‐rate Encoder of QC‐LDPC Codes Based on FPGA for WIMAX Standard

Wang, Xiumin; Ge, Tingting; Li, Jun; Su, Chen; Hong, Fangzhou

doi:10.1049/cje.2017.01.006

Cited by 15 publications

(9 citation statements)

References 10 publications

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“…These outputs are the same as the results from Eqs. 12, (13), and (14). Therefore, the characteristics of the generator matrix can be considered to use in the process of our encoding optimization algorithm for a general case.…”

Section: Proposed Oea For Spcmentioning

confidence: 99%

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An optimized encoding algorithm for systematic polar codes

Wang

et al. 2019

J Wireless Com Network

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Many different encoding algorithms for systematic polar codes (SPC) have been introduced since SPC was proposed in 2011. However, the number of the computing units of exclusive OR (XOR) has not been optimized yet. According to an iterative property of the generator matrix and particular lower triangular structure of the matrix, we propose an optimized encoding algorithm (OEA) of SPC that can reduce the number of XOR computing units compared with existing non-recursive algorithms. We also prove that this property of the generator matrix could extend to different code lengths and rates of the polar codes. Through the matrix segmentation and transformation, we obtain a submatrix with all zero elements to save computation resources. The proportion of zero elements in the matrix can reach up to 58.5% from the OEA for SPC when the code length and code rate are 2048 and 0.5, respectively. Furthermore, the proposed OEA is beneficial to hardware implementation compared with the existing recursive algorithms in which signals are transmitted bidirectionally.

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Section: Proposed Oea For Spcmentioning

confidence: 99%

“…However, the latency and resource consumption were twice than that of the hardware implementation with NSPC. Wang et al found a method that utilized the property of parity check matrix to reduce the computational units [14][15][16]. This approach can be utilized for both SPC and NSPC to reduce computational units.…”

Section: Introductionmentioning

confidence: 99%

An optimized encoding algorithm for systematic polar codes

Wang

et al. 2019

J Wireless Com Network

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“…In [ 9 ], a multigigabit QC-LDPC encoding architecture is proposed; this architecture leverages the inherent parallelism of QC structural by simultaneously processing multiple bits according to optimal scheduling. In [ 10 ], a high-efficiency multi-rate encoder for IEEE 802.16e QC-LDPC codes is proposed; this design uses the double diagonal structure in the parity matrix to avoid the inverse matrix operation that requires a lot of calculations. Meanwhile, a parallel matrix vector multiplication structure and storage compression are used to increase the encoding speed and significantly reduce the number of storage bits required.…”

Section: Introductionmentioning

confidence: 99%

Low-Latency QC-LDPC Encoder Design for 5G NR

Tian

Bai

Liu

2021

Sensors

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In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

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“…However, the use of a large number of I/O pins to generate the parity check bits may exceed the resource limit of field programmable gate array (FPGA). In [20], an efficient multi-rate encoder featured with high encoding speed and minimum hardware usage is proposed for the IEEE 802.22 Wireless Regional Area Network (WRAN) standard. In fifth generation (5G) new radio (NR), the bidiagonal architecture proposed in [21] is exploited to reduce the complexity of the encoder.…”

Section: Introductionmentioning

confidence: 99%

Low-complexity encoder implementation for LDPC codes in CCSDS standard

Chen

Han

2021

IEICE Electron. Express

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The traditional direct LDPC encoder in CCSDS standard for space application needs to store the first row in each submatrix of the generator matrix, making the circuit implementation complex. To solve this problem, a low-complexity encoder for LDPC codes is implemented in this letter. The encoder stores the vector in random-access memory (RAM). To implement the multiplication of sparse matrix and vector with limited hardware resources, the encoder takes the row indexes of nonzero entries in each column of sparse matrix as the write address of the RAM. Moreover, the shift-register-adder-accumulator is exploited to implement the multiplication of the dense core matrix and the vector, greatly reducing the storage and computation complexity. The LDPC encoder with the code rate of 1/2 in the CCSDS standard is implemented on Xilinx XC6VLX240T FPGA chip, and the implementation results indicate that the proposed encoder consumes 50% less hardware resources than the traditional direct encoder.

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Efficient Multi‐rate Encoder of QC‐LDPC Codes Based on FPGA for WIMAX Standard

Cited by 15 publications

References 10 publications

An optimized encoding algorithm for systematic polar codes

An optimized encoding algorithm for systematic polar codes

Low-Latency QC-LDPC Encoder Design for 5G NR

Low-complexity encoder implementation for LDPC codes in CCSDS standard

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