Efficient power Intent validation using loosely-timed simulation models

Abstract

Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far.In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a "loosely-timed" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.

Architectural low-power design using transaction-based system modeling and simulation

“…Our power-aware TLM simulation front-end incorporates several tasks; (i) power intent extraction, (ii) non-intrusive TLM model instrumentation, and (iii) efficient cosimulation to reflect voltage related functional deviations. We already published a proof of concept framework in [17] based on IEEE 1801-2013 (UPF) parsing and a SystemC class library of low-power design constructs. Hence, we automatically translate UPF compliant specifications into executable power intent models parallel to the TLM design.…”