Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths

Sauer, Matthias; Reimer, Sven; Schubert, Tobias; Polian, Ilia; Becker, Bernd

doi:10.7873/date.2013.100

Cited by 16 publications

(7 citation statements)

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“…Recently, SAT-based ATPG [17,22,30] and optimization methods based on efficient SAT solving engines attracted attention in the field of test generation [4,5,7,8,27], i.e. by reducing aborts, maximizing fault detection and powerdroop conditions.…”

Section: Related Prior Workmentioning

confidence: 99%

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Eggersglüβ

2014

J Electron Test

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Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic Xfilling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.

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Section: Related Prior Workmentioning

confidence: 99%

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Eggersglüβ

2014

J Electron Test

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“…In general, the computation time of test generation is depending on the scale and complexity of a circuit. In order to reduce the test generation search space, many methods have been proposed in the last two or three decades [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Search Space Reduction for Low-Power Test Generation

Miyase

Sauer

Becker

et al. 2013

2013 22nd Asian Test Symposium

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Ongoing research to shrink feature sizes of LSI circuits leads to an always increasing number of logic gates in a circuit. In general, the complexity of test generation depends on the size of a circuit. Furthermore, modern test generation methods have to consider power reduction in addition to fault detection, since excessive power caused by testing may result in overtesting. In this work, we propose a method to reduce the computation time of low-power test generation. The proposed method specifies gates which will cause power issues, consequently reducing the search space for X-filling technique. The reduction of search space for Xfilling also further minimizes the amount of switching activity. Experimental results for circuits of OpenCores provided by IWLS2005 benchmarks show that the proposed method achieves both a reduced computation time and at the same time increased power reduction compared to previous methods.

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“…This can be used to merge test patterns or increase the compression ability. The SAT-based ATPG approaches in [12] and [13] use optimization procedures to produce a compact test set. The technique in [12] explicitly targets a single fault and encodes additional local fault detection conditions for undetected faults into the SAT instance.…”

Section: Introductionmentioning

confidence: 99%

“…However, this technique partly relies on an runtime-intensive classical dynamic compaction scheme using an additional target generator. The technique in [13] works as a post-process. The necessary assignments of sensitized paths are extracted from a pre-generated test set and an optimization procedure is applied to generate tests which detects as many of these paths as possible.…”

Section: Introductionmentioning

confidence: 99%

Optimization-based multiple target test generation for highly compacted test sets

Eggersglüβ

Schmitz

Krenz-Baath

et al. 2014

2014 19th IEEE European Test Symposium (ETS)

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Test compaction is an important aspect in the postproduction test since it is able to reduce the test data and the test costs, respectively. Current ATPG methods treat all faults independently from each other which limits the test compaction capability. This paper proposes a new optimization based SAT-ATPG for compact test set generation. Robust solving algorithms are leveraged to determine fault groups which can be detected by the same test. The proposed technique can be used during initial compact test generation as well as a post-process to increase the compactness of existing test sets, e.g. generated by commercial tools, in an iterative manner. Experimental results on industrial circuits and academic benchmarks show that this technique is able to significantly reduce the pattern count down to 40% for the initial test generation and down to 30% for the iterative reduction.

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Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths

Cited by 16 publications

References 0 publications

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Search Space Reduction for Low-Power Test Generation

Optimization-based multiple target test generation for highly compacted test sets

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