Efficient synthesis of approximate threshold logic circuits with an error rate guarantee

Lai, Yung-An; Lin, Chih-Long; Wu, Chia-Cheng; Chen, Yung-Chih; Wang, Chun-Yao

doi:10.23919/date.2018.8342111

Cited by 7 publications

(3 citation statements)

References 35 publications

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“…Other papers on approximate logic synthesis have been published over the past three years. In [26], the authors present an interesting integration between threshold logic and approximate computing and propose a synthesis algorithm to obtain cost-efficient approximate threshold logic circuits with an error rate guarantee. A new approximate logic synthesis technique based on Boolean matrix factorization is proposed in [19].…”

Section: Related Workmentioning

confidence: 99%

“…In recent years there has been an increasing flow of publications to investigate approximate logic synthesis, from one side adapting to the new scenario the conceptual tools already developed for standard exact logic synthesis, from the other side addressing the specific issues such as modeling the acceptable errors. We refer to the next section on previous work for a tentative survey of relevant literature (see for instance [8], [15], [26], [27], [28], [29], [34], [35], [39]).…”

Section: Introductionmentioning

confidence: 99%

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Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis

Bernasconi

Ciriani

Villa

2022

IEEE Trans. Comput.

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Approximate synthesis is a recent trend in logic synthesis where one changes some outputs of a logic specification, within the error tolerance of a given application, to reduce the complexity of the final implementation. We attack the problem by exploiting the allowed flexibility in order to maximize the regularity of the specified Boolean functions. Specifically, we consider two types of regularity: symmetry and D-reducibility, and contribute two algorithms to find, respectively, a symmetric and a D-reducible approximation of a given target function f , within the given error rate threshold if possible. When targeting symmetry, we characterize and compute polynomially the closest symmetric approximation, i.e., the symmetric function obtained by injecting the minimum number of errors in the original incompletely specified Boolean function, with an unbounded number of errors; then, we discuss strategies to achieve partial symmetrization of the original specification while satisfying given error bounds. Finally, we present a polynomial heuristic algorithm to compute a D-reducible approximation of an incompletely specified target function, under a bit error metric. Experimental results on classical and new benchmarks confirm the effectiveness of the proposed approaches.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis

Bernasconi

Ciriani

Villa

2022

IEEE Trans. Comput.

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“…In recent years, many heuristic techniques for synthesizing approximate logic circuits have been investigated with promising results, see for instance [3], [5], [14], [15], [16], [20], [21], [22]. They derive approximate variants of a given combinational Boolean function, by modifying some of its outputs so that the modified circuit has a reduced complexity and power consumption, while the error is within the tolerance bounds (targeting two-level logic, XOR-AND-OR forms, multi-level logic, etc.…”

Section: Introductionmentioning

confidence: 99%

Approximate Logic Synthesis by Symmetrization

Bernasconi

Villa

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Approximate synthesis is a recent trend in logic synthesis that changes some outputs of a logic specification to take advantage of error tolerance of some applications and reduce complexity and consumption of the final implementation. We propose a new approach to approximate synthesis of combinational logic where we derive its closest symmetric approximation, i.e., the symmetric function obtained by injecting the minimum number of errors in the original function. Since BDDs of totally symmetric functions are quite compact, this approach is particularly convenient for BDD-based implementations, such as networks of MUXes directly mapped from BDDs. Our contribution is twofold: first we propose a polynomial algorithm for computing the closest symmetric approximation of an incompletely specified Boolean function with an unbounded number of errors; then we discuss strategies to achieve partial symmetrization of the original specification while satisfying given error bounds. Experimental results on classical and new benchmarks confirm the efficacy of the proposed approach.

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