Efficient thermal placement of standard cells in 3D ICs using a force directed approach

Goplen, B.; Sapatnekar, Sachin S.

doi:10.1109/iccad.2003.1257591

Cited by 173 publications

(129 citation statements)

References 8 publications

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“…The force directed method is a well known technique used for cell placement [40], where repulsive or attractive forces are placed on the cells as if these cells are connected through a system of springs. The force directed method has been extended to incorporate the thermal objective during the placement process [41]. In this approach, repulsive forces are applied to those blocks that exhibit high temperatures (i.e., "hot blocks") to ensure that the high temperature blocks are placed at a greater distance from each other.…”

Section: Placement For 3-d Circuitsmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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Section: Placement For 3-d Circuitsmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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show abstract

“…The force directed method is a well-known technique used for cell placement [83], where repulsive or attractive forces are placed on the cells as if these cells are connected through a system of springs. The force directed method has been extended to incorporate the thermal objective during the placement process [84]. In this approach, repulsive forces are applied to those blocks that exhibit high temperatures (i.e., Bhot blocks[) to ensure that the high-temperature blocks are placed at a greater distance from each other.…”

Section: Placement For 3-d Circuitsmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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“…Other techniques for efficiently solving the thermal PDE for on-chip thermal analysis include techniques based on finite elements 28) and Green functions 92),101) . The on-chip thermal profile of a circuit can be optimized using a variety of techniques.…”

Section: Temperaturementioning

confidence: 99%

Variability and Statistical Design

Sapatnekar

2008

IPSJ Transactions on System LSI Design Methodology

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With each technology generation, the effects of on-chip variations are seen to more profoundly affect digital circuit behavior. These variations may arise from fluctuations attributed to the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield, as well as variations in the environmental operating conditions (e.g., supply voltage or temperature) after the circuit is manufactured, which impact the performance of the design. These effects can cause unacceptable alterations in circuit performance parameters such as timing and power, and variation-tolerant design is imperative for next-generation designs. This paper overviews research in this area, describing methods for the analysis and optimization of statistical effects.

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Efficient thermal placement of standard cells in 3D ICs using a force directed approach

Cited by 173 publications

References 8 publications

Physical Design Issues in 3-D Integrated Technologies

Physical Design Issues in 3-D Integrated Technologies

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Variability and Statistical Design

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