ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon

Sylvester, Dennis; Blaauw, David; Karl, Eric

doi:10.1109/mdt.2006.145

Cited by 84 publications

(45 citation statements)

References 9 publications

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“…In a reconfigurable architecture, recovery entails isolating defective module(s) and incorporating spare structures as needed. Support for reconfiguration can be achieved at various granularities, from ultrafine grain systems [7,8] that have the ability to replace individual logic gates to coarser designs that focus on isolating entire processor cores [1,2,[9][10][11][12][13][14]21]. This choice presents a trade-off between complexity of implementation and potential lifetime enhancement [15,16].…”

Section: Related Workmentioning

confidence: 99%

“…Therefore, I have only analyzed dynamic power dissipation in this paper. 2 Number of incoming from other core can be 1 if the SN architecture supports 'stage sharing'. However, 'stage sharing' is optional technique of the SN architecture and it only shows very trivial improvement [5].…”

Section: Motivationmentioning

confidence: 99%

“…With the recent popularity of multi-core systems, traditional fault-tolerant core-level approaches have been able to leverage the inherent redundancy present in large chip multiprocessors (CMPs) [1,2]. However, both the historical designs and their modern incarnations, because of their emphasis on core-level redundancy, incur high hardware overhead and can only tolerate a small number of defects [2].…”

Section: Introductionmentioning

confidence: 99%

“…However, both the historical designs and their modern incarnations, because of their emphasis on core-level redundancy, incur high hardware overhead and can only tolerate a small number of defects [2]. With the increasing defect rate in semiconductor technology, it will not be uncommon to see a rapid degradation in throughput for these systems as single device failures cause entire cores to be decommissioned, often times with the majority of the core still intact and functional [3,4].…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Kim

2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/ power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

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Section: Related Workmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Kim

2011

JSTS:Journal of Semiconductor Technology and Science

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“…Information from in situ monitors is much more trustable than indirect measures [2]. Multiuse sensors that can monitor performance, degradation, and power consumption as the circuit ages have become critical [3]. However, allocating an arbitrarily large number of such monitors will not only create a significant area overhead, but routing the data from the sensor registers to a central processing unit will also pose a challenge [4].…”

Section: Introductionmentioning

confidence: 99%

On-chip Monitoring: A Light-Weight Interconnection Network Approach

Ituero

López‐Vallejo

Marcos

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Current nanometer technologies are subjected to several adverse effects that seriously impact the yield and performance of integrated circuits. Such is the case of within-die parameters uncertainties, varying workload conditions, aging, temperature, etc. Monitoring, calibration and dynamic adaptation have appeared as promising solutions to these issues and many kinds of monitors have been presented recently. In this scenario, where systems with hundreds of monitors of different types have been proposed, the need for light-weight monitoring networks has become essential. In this work we present a light-weight network architecture based on digitization resource sharing of nodes that require a time-todigital conversion. Our proposal employs a single wire interface, shared among all the nodes in the network, and quantizes the time domain to perform the access multiplexing and transmit the information. It supposes a 16% improvement in area and power consumption compared to traditional approaches.

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