Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data

Mizuno, Masayuki; Dally, William J.; Onishi, H.

doi:10.1109/isscc.2001.912667

Cited by 18 publications

(24 citation statements)

References 2 publications

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“…This circuit consumes a slightly greater area and power than the circuit in Figure 2, but offers a reliable error-free operation under varying frequencies. Both implementations of the control block in Figure 2 and Figure 3 are more efficient than the design using a conventional repeater-inserted control line [25], as the control block provides the following advantages: (1) The control circuit behaves as a delay module as well as a repeater for the congestion signal. Unlike conventional repeaters, the control circuit shown in Figure 3 operates accurately at variable clock speeds and enables error-recovery in case of timing errors.…”

Section: Control Block Implementationmentioning

confidence: 99%

“…Research into the optimization of these repeaters has shown that the repeaters can also be designed to sample and hold data when required thereby providing storage in addition to their conventional functionality [25]. Therefore, with repeaters as potential buffer elements, we can use them as buffers along the links by triggering a control signal at high network loads when there are no more buffers in the router.…”

Section: Introductionmentioning

confidence: 99%

“…At the links, we deploy circuit level enhancements to the existing repeaters so that they double as buffers when required. While using the repeaters to sample and hold data is well known [25], we evaluate two control techniques that enable the repeaters to adaptively function as buffers during congestion. While the first technique using a switched capacitor is suitable for designs with low implementation overhead, the second circuit employs a self-correcting double-sampling technique to guarantee error-free operation at high frequencies at a marginally higher power consumption.…”

Section: Introductionmentioning

confidence: 99%

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iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Kodi

Sarathy

Louri

2008

2008 International Symposium on Computer Architecture

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Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efficient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dualfunction links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques.

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Section: Control Block Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Kodi

Sarathy

Louri

2008

2008 International Symposium on Computer Architecture

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“…In order to cope with the long link delays, a latency-insensitive design approach is presented in [8] and [9]. The use of repeaters to store data in an asynchronous link design is presented in [35]. The buffering mechanism on the wires in the scheme is asynchronously controlled by the receiver and is not integrated with the switches of the NoC.…”

Section: Previous Workmentioning

confidence: 99%

Timing-Error-Tolerant Network-on-Chip Design Methodology

Tamhankar

Murali

Stergiou

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on chip (NoCs), has been proposed recently to address the communication issues of SoCs. As the geometries of devices approach the physical limits of operation, NoCs will be susceptible to various noise sources such as crosstalk, coupling noise, process variations, etc. Designing systems under such uncertain conditions become a challenge, as it is harder to predict the timing behavior of the system. The use of conservative design methodologies that consider all possible delay variations due to the noise sources, targeting safe system operation under all conditions will result in poor system performance. An aggressive design approach that provides resilience against such timing errors is required for maximizing system performance. In this paper, we present T-error, which is a timing-error-tolerant aggressive design method to design the individual components of the NoC (such as switches, links, and network interfaces), so that the communication subsystem can be clocked at a much higher frequency than a traditional conservative design (up to 1.5× increase in frequency). The NoC is designed to tolerate timing errors that arise from overclocking without substantially affecting the latency for communication. We also present a way to dynamically configure the NoC between the overclocked mode and the normal mode, where the frequency of operation is lower than or equal to the traditional design's frequency, so that the error recovery penalty is completely hidden under normal operation. Experiments on several benchmark applications show large performance improvement (up to 33% reduction in average packet latency) for the proposed system when compared to traditional systems.Index Terms-Aggressive design, networks on chip (NoCs), systems on chip (SoCs), timing errors.

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“…Long links suffer from an excessive power consumption and large latency, that makes them costly or even unfeasible. To minimize the impact of long links, in [72][73][74] long links are replaced by elastic buffers, that is, buffered links where a trade-off between latency and power consumption is made, because a flit requires several hops to traverse an elastic buffer. In [75], authors focus on 3D technology as an ideal scenario to implant high-radix topologies because long 2D links evolve to short and power efficient 3D vias.…”

Section: Long Link Issuesmentioning

confidence: 99%

Floorplan-Aware High Performance NoC Design

Pérez¹

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Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data

Cited by 18 publications

References 2 publications

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Timing-Error-Tolerant Network-on-Chip Design Methodology

Floorplan-Aware High Performance NoC Design

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