Electrical characterisation of oxides grown in different RTP ambients

Brazzelli, D.; Ghidini, G.; Crivelli, B.; Zonca, R.; Bersani, M.; Xing, G. C.; Miner, G.; D’Astici, N; Kuppurao, Satheesh; Lopes, D.

doi:10.1016/s0026-2714(99)00268-1

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2017

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“…Embedded Flash memories down-scaling is only possible with the optimization of logic and high voltage devices together with the memory cell. One optimization path is the introduction of nitrided oxide to enhance the oxide robustness versus electrical stress and to reduce dopant inter-diffusion [1] [2]. Previous studies have shown the importance of the nitrogen distribution in the tunnel oxide and the relationship between process temperature and nitrogen bonding [3] [7].…”

Section: Introductionmentioning

confidence: 99%

Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array

Kempf

Mantelli

Maugain

et al. 2017

2017 IEEE International Integrated Reliability Workshop (IIRW)

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The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

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Section: Introductionmentioning

confidence: 99%