Electrical characterization and structure investigation of quad flat non-lead package for RFIC applications

Optimal laser-cutting parameters for QFN packages by utilizing artificial neural networks and genetic algorithm

“…1 (Li et al, 2007). A QFN package is a plastic encapsulated lead-frame based Chip Scale Package (CSP) with the lead pad on the bottom of the package to provide electrical interconnection with the printed circuit board (PCB) (Chen et al, 2003). Several QFN chips are packaged in an array form and must be separated into individual QFN chips before mounting on different printed-circuit boards.…”

“…It consists of a plastic encapsulated package with a copper lead frame substrate. This packaging technology, which has many advantages, such as less size and weight, good electrical performance and high speed and frequency, has been applied widely in many products (Chen et al, 2003). In cutting QFN ICs, the conventional technology using diamond saw has the advantage of highincluding the effect of laser-cutting speed on surface temperature (Rajendran and Pate, 1988), on surface quality (Neimeyer et al, 1993), and on surface roughness (Rajaram et al, 2003), and the effect of laser frequencies on HAZ (Kaebernick et al, 1998).…”

Natural convection on inclined QFN32 electronic package generating constant volumetric heat flux

“…The authors propose optimized sequential tests for the qualification package, in which the temperature plays an important role. Chen et al [20] propose a wideband equivalent circuit model of QFN packages for radio frequency (RF) applications which are widely used in domestic devices such as cellular phones. The numerical study shows that the best structure of the QFN32 package for RF applications consists of double bonding wires with a lower dielectric-constant molding compound and larger die-pad.…”

The use of grey relational analysis to determine laser cutting parameters for QFN packages with multiple performance characteristics

“…The structure of a QFN strip is an array form of chips packaged by bonding with epoxy on the copper lead frame substrate [1]. Therefore, the chips need to be separated into an individual IC before being mounted onto a printed-circuit board.…”