Electrical properties of Si nanocrystals embedded in an ultrathin oxide

Abstract

We investigate Si nanocrystals fabricated by the rapid thermal oxidation (RTO) of an ultrathin chemical vapour deposition (CVD) amorphous Si (a-Si:H) film. It is found from the transmission electron microscope (TEM) observation that the ultrathin RTO film contains Si nanocrystals of around or less than 5 nm in size. The dynamic electrical conduction measurement of the RTO diode structure including the Si nanocrystals reveals novel features such as the N-shaped tunnel current versus gate voltage characteristics and the hysteresis. It is also found that the gate voltages at the first and second current rise are fixed and the current reduction in the fixed time interval is observed at the constant gate voltage. These findings can be explained by the fixed-amount electron charging effect at the Si nanocrystals and the consequent screening effect on the tunnel current flowing through the diode structure.

Charging effects in Ge nanocrystals embedded in SiO2 matrix for non volatile memory applications

“…This result is reproducible only for the two samples with the thinnest tunnel oxides (samples A and B). These peaks have been observed by other authors at low [17] temperature and at the ambient one [15,16] and are attributed either to the resonant tunneling or to charging effects in the nanocrystals. In our case the first assumption is excluded because of the dissymmetry of the studied structure [13,14].…”

Transient charging current measurements and modelling in silicon nanocrystal floating gate devices

“…Such peaks in I G -V G curves have already been observed and differently interpreted by other research teams [10,11,21]. In Refs.…”

“…Moreover, in the short term, lithographic patterning is expected to be avoided by the industry at the nanometer scale. In that context, few silicon based bottom-up techniques have been investigated: annealing of a thin silicon layer deposited onto an insulator [10][11][12], low pressure chemical vapour deposition (LPCVD) of silicon clusters onto an insulator layer [13][14][15], aerosol synthesis [6,22] and thermal demixtion of a silicon rich oxide (SRO) layer. SRO may be obtained by low energy 28 Si + ions into a thermal oxide layer [16][17][18] or by CVD (chemical vapor deposition) with such parameters that a SiO X<2 layer is elaborated [19,20].…”

Silicon Nanocrystal Flash Memory

“…Size, density, and location of the nc-Si dots were demonstrated to correlate with the dose and acceleration of ion as well as the subsequent annealing conditions, however hard it may be to make precise control [57]. Other preparation methods that have been used for forming nc-Si dots rely on crystallization of amorphous silicon [58] or aerosol nc-Si dots from silane pyrolysis [31] and various sputtering techniques [59]. It is worthwhile to mention that most of sputtering approaches need postannealing a temperature up to 1000 C.…”