Electrical Studies on Annealed  D 2 Plasma‐Exposed Silicon

Abstract

Defects introduced by annealing in D2 plasma-exposed, boron-doped silicon have been studied by means of deep level transient spectroscopy (DLTS) and capacitance-voltage measurements. A hole trap at Ev = 0.48 eV (Ev being the edge of the valence band) seen after annealing at 175~ is tentatively assigned to a defect containing a vacancy. This hole trap anneals out following heat-treatment at 225~ Other hole traps at Ev + 0.30 eV and Ev + 0.50 eV are observed in the samples following annealing at temperatures higher than 475~ In the annealing temperature range 325-425~ an observed broad DLTS band is attributed to complex defect structures in which deuterium atoms are bonded to an as-yet unidentified defect core. These structures are suggested to differ in the number of deuterium atoms bonded to the core: Each of these structures gives rise to a hole trap(s) in the energy range Ev + 0.4 eV to Ev + 0.6 eV within the forbidden gap. A nonzero residual DLTS signal seen in all the samples annealed at 525~ or below is proposed to be due to extended defects or platelets, confined to the first few microns region close to the plasma-exposed surface.Reactive ion etching (RIE) is widely acknowledged as a useful process in the fabrication of small dimension semiconductor devices (1, 2). During this process, the ion bombardment of the surfaces and the contamination from the reactive ion species are known to produce complex defects in the damaged near-surface region of silicon, as observed by transmission electron microscopy (TEM) (3) and photoluminescence (PL) (4-6). Secondary ion mass spectrometry (SIMS) profiles, on samples treated in a deuterium plasma, show an Unexpectedly large concentration of deuterium deep into Si (7). Effects on the electrical behavior of the near-surface silicon crystal have also been reported from studies on the capacitance voltage (CV) and current-voltage (IV) characteristics of metal oxide semiconductor (MOS) structures formed on RIE-etched silicon surfaces (8,9). Using DLTS measurements performed on CF4/H2 RIE-etched p-type (10) or n-type (11) silicon, various carrier traps were observed. Tentative assignments for some of these traps were also made. In a recent study (12) using DLTS, we have shown that a hole trap at 0.44 eV above the valence band is detected directly after plasma exposure, using deuterium plasma, of boron-doped silicon and increases in concentration as the sample is annealed to 200~ This trap was tentatively attributed to a vacancyrelated defect complex. The contamination of the substrate with heavy metals during etching has also been detected using the DLTS technique (13, 14).The study of RIE-induced damage directly after treatment has received much attention recently. However, we feel that the investigation of the evolution of this damage following high-temperature annealing is also of prime importance. This is due to several reasons, some of which are the following:1. It is of great technological interest to study the annealing of the damage centers resulting from plasma treatme...