1999
DOI: 10.1088/1464-4258/1/2/029
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Electrical, thermal and optomechanical packaging of large 2D optoelectronic device arrays for free-space optical interconnects

Abstract: Innovative approaches to the design of a high-performance package module accommodating a 32 × 32 array of surface-active devices indium bump bonded to a 8 × 8 mm 2 VLSI chip are presented. Electrical, thermal and optomechanical design considerations are discussed and experimental performance results of a prototype implementation are described. The package module supports 139 impedance-controlled signal connections as well as active temperature stabilization of the optoelectronic VLSI chip. The package module i… Show more

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Cited by 14 publications
(3 citation statements)
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“…Simulation results show that grouping the optical elements within modules gives better misalignment tolerances. 21,24 For example, the VCSEL or the microlens alone have a lateral misalignment tolerance of Ϯ 2.5 m. Once they are attached to each other, the resulting chip module has a tolerance of Ϯ 25 m. The alignment of the microlenses to the VCSELs is the most critical task. However, this tolerance was achievable through the use of active alignment.…”
Section: Results Of Misalignment Tolerance Analysismentioning
confidence: 99%
See 1 more Smart Citation
“…Simulation results show that grouping the optical elements within modules gives better misalignment tolerances. 21,24 For example, the VCSEL or the microlens alone have a lateral misalignment tolerance of Ϯ 2.5 m. Once they are attached to each other, the resulting chip module has a tolerance of Ϯ 25 m. The alignment of the microlenses to the VCSELs is the most critical task. However, this tolerance was achievable through the use of active alignment.…”
Section: Results Of Misalignment Tolerance Analysismentioning
confidence: 99%
“…This enabled each block to be individually characterized and results in better misalignment tolerances of the components. 21,24 The design of the optical link was guided by the following requirements. First, the pitch between the active elements on the VLSI-OE chips was fixed to 125 m. The number of VCSELs and detectors was specified to be 512 devices and the center-tocenter separation of the chips was 83 mm.…”
Section: Optical Designmentioning
confidence: 99%
“…Figure 12 also draws a comparison between our OSPP prototype and other recent optoelectronic system demonstrators ͑photonic switching systems, free- 38 and by use of a compact, rugged optical hardware module as described in Ref. 39. We assumed a 5-SPA system with 2ϫ diffractive optical elements that interconnect adjacent arrays ͑an architecture equivalent to that of the AT&T͞93 demonstrator͒.…”
Section: Electrical Power Budget and Thermal Limitationsmentioning
confidence: 99%