Abstract:It has been well known for years that as the critical feature size within a chip keeps shrinking, design and optimization among power, heat and performance would become even challenging. On one hand, the electrical functionalities of the devices are closely coupled with temperature and power distributions. On the other hand, the devices within the chip are not totally isolated and confined-the connection and interaction with the environments such as the package, board, and enclosure cannot be ignored especiall… Show more
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