Electromechanical Simulation of Switching Characteristics for Nanoelectromechanical Memory

Abstract

The static switching properties and readout characteristics of proposed high-speed and nonvolatile nanoelectromechanical (NEM) memory devices are investigated. By conducting a three-dimensional finite element mechanical simulation combined with an electrostatic analysis, we analyze the electromechanical switching operation of a mechanically bistable NEM floating gate by applying gate voltage. We show that switching voltage can be reduced to less than 10 V by reducing the zero-bias displacement of the floating gate and optimizing the cavity structure to improve mechanical symmetry. We also analyze the electrical readout property of the NEM memory devices by combining the electromechanical simulation with a drift-diffusion analysis. We demonstrate that the mechanically bistable states of the floating gate can be detected via the changes in drain current with an ON/OFF current ratio of about 3 Â 10 4 .

Scaling Analysis of Nanoelectromechanical Memory Devices

“…19) We also performed a three-dimensional finite element method (FEM) simulation and obtained the switching and readout operations for NEMS memory. 20,21) However, the length of the floating gate used in ref. 21 was 1 mm.…”

“…In past analysis, 21) we obtained the electric property of the NEMS memory as shown ''Original'' in Fig. 3(a).…”

“…First, we analyzed the electrical readout characteristics for miniaturized structures from theoretical equations before performing a numerical simulation. In past analysis, 21) we obtained the electric property of the NEMS memory as shown ''Original'' in Fig. 3(a).…”

Hybrid numerical analysis of a high-speed non-volatile suspended gate silicon nanodot memory (SGSNM)

“…The self-buckled FG was made with a SiNDs monolayer sandwiched between SiO 2 layers and doubly clamped in a cavity integrated on the readout MOSFET. The SiNDs embedded in the FG were initially charged with electron injection from top control gate before removing an upper sacrificial α-Si layer [12]. The self buckled FG flip-flops between its mechanically-bistable states by applying a voltage to the top control gate, which changes the MOSFET surface potential, resulting in the shift of the threshold voltage.…”

“…As the P/E processes do not involve the charge tunnelling via the gate oxide layer, there is no degradation of this layer, and therefore no leakage current is anticipated. However, this NEM memory has inherently an unfavourable tradeoff between the P/E voltage and readout current ON/OFF ratio and a recent study indicates that the scalability deteriorates when the beam length is scaled down to less than 100 nm [12]. In Fig.…”