Electromigration and Thermal Storage Study of Barrierless Co Vias

Pedreira, O. Varela; Croes, Kristof; Zahedmanesh, Houman; Vandersmissen, K.; Veen, Marleen H. van der; Gonzalez, V. Vega; Dictus, Dries; Zhao, Larry; Kolies, A.; Tőkei, Zs.

doi:10.1109/iitc.2018.8430396

Cited by 19 publications

(15 citation statements)

References 3 publications

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“…51 Ru interconnects allow for a barrierless integration owing to its high cohesive energy and its better resistance to oxidation. 52 However, the adhesion of Co and Ru to a dielectric interlayer is a problem. TiN has been used for enhancing the adhesion of Ru to SiO 2 .…”

Section: Resultsmentioning

confidence: 99%

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Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI

Zhan

Oda

et al. 2020

ACS Appl. Mater. Interfaces

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Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1 × 10 −8 to 1 × 10 −7 m 2 K W −1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.

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Section: Resultsmentioning

confidence: 99%

“…Only a 1-nm-thick barrier film is required for Co interconnects . Ru interconnects allow for a barrierless integration owing to its high cohesive energy and its better resistance to oxidation . However, the adhesion of Co and Ru to a dielectric interlayer is a problem.…”

Section: Resultsmentioning

confidence: 99%

Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI

Zhan

Oda

et al. 2020

ACS Appl. Mater. Interfaces

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“…It is two orders of magnitude lower than Cu. While Co vias may be EM immortal, the lack of a barrier may induce diffusion along the Co/dielectric interfaces and Co/Cu intermixing [64]. The physics-based compact EM model introduced in this section is also applicable to interconnects based on new materials such as Co and Ru only if the diffusion coefficients and microstructures are extracted from experiment result [65].…”

Section: Model Applicationsmentioning

confidence: 99%

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

2022

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The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

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“…Several reports have also demonstrated the feasibility of the via prefill concept using the electroless deposition (ELD) technique Co as material to pre-fill vias [ 259 , 260 , 261 ]. A main benefit of having Co via is the reduction of the via resistance.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Electromigration and Thermal Storage Study of Barrierless Co Vias

Cited by 19 publications

References 3 publications

Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI

Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

State of the Art and Future Perspectives in Advanced CMOS Technology

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