Electromigration-induced drift in damascene and plasma-etched Al(Cu). I. Kinetics of Cu depletion in polycrystalline interconnects

Abstract

In this work, a direct and quantitative comparison is presented on the rate of electromigration-induced Cu depletion for polycrystalline damascene and reactive ion etched ͑RIE͒ Al͑Cu͒. Kinetic data are derived from the incubation time, obtained from drift characteristics of both unpassivated and passivated Blech-type test structures between 155 and 230°C. Since the incubation time represents the time necessary for the electron wind to deplete the critical length free of Cu, both electromigration ͑EM͒-threshold and the rate of Cu depletion was systematically investigated. For the latter specific microstructural features, related to Al 2 Cu precipitate morphology and distribution, are discussed. EM-threshold on the other hand is a more intrinsic characteristic of the interconnect, depending on geometrical and mechanical properties ͑like aspect ratio and encapsulation͒. For geometrically equivalent, unpassivated structures, it was found that the improvement in incubation time for the damascene implementation is predominantly controlled by a higher critical length caused by its encapsulation inside the dielectric. For passivated structures, the impact of encapsulation on enlarging the maximum elastic stress buildup becomes similar. As a result, the difference in threshold between passivated damascene and RIE was observed to decrease. The incubation time in passivated structures becomes more importantly controlled by the kinetics of Cu depletion. It is demonstrated that it is most effective to maximize the degree of intergranular precipitation to retard the Cu depletion rate in polycrystalline structures. Implications on the relative EM performance under operating conditions for damascene and RIE Al͑Cu͒ are also discussed.

Reliability and early failure in Cu/oxide dual-damascene interconnects

“…As a consequence, the explicit flux divergence for Al-based EM is located over the top of the cathode end (electron source) W via, and EM voiding is often located there in submicron interconnects with bamboo-type grains. 4,9,[11][12][13][14] In comparison, the DD configuration (in Cu or Al versions) is differently constructed. [15][16][17] For the case of Cu DD interconnects, the upper-level (M2) trench and connecting via (V1) to the lower-level trench (M1) are simultaneously prepared before Cu filling to form the DD interconnect (Fig.…”

Effects of deposition conditions of Al and Ti underlayer on electromigration reliability for deep-submicron interconnect metallization

“…The presence of an incubation time thereby relies on the well-known retarding effect of Cu on the Al grain boundary diffusivity, which controls the dominant mass transport if the interconnect width is well above the median grain size. 8 The Al alloy interconnections stacked with Ti such as Ti\Al-0.5wt.%Cu\Ti\TiN have been widely used in VLSI circuits to realize both a high EM resistance and a low via resistance. The formation of an Al intermetallic compound such as the TiAl 3 alloy above or below the Al metal layer is known to be effective in preventing EM-related failures.…”

Effects of texture and grain structure on electromigration lifetime of Al−Cu interconnects

“…For polycrystalline Al-Cu, mass transport is well documented [7] as occurring in two sequential stages: an incubation period through Cu depletion beyond a critical length, followed by the actual Al drift stage. The presence of an incubation time thereby relies on the well-known retarding effect of Cu on Al grain boundary diffusivity, which controls the dominant mass transport if the interconnect width is well above the median grain size [8].…”