Electron trapping at SiO₂/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis

Abstract

Studying the electrical and structural properties of the interface of the gate oxide (SiO) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimising the performances of metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper, near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated combining transient gate capacitance measurements (C-t) and state of the art scanning transmission electron microscopy in electron energy loss spectroscopy (STEM-EELS) with sub-nm resolution. The C-t measurements as a function of temperature indicated that the effective NIOTs discharge time is temperature independent and electrons from NIOTs are emitted toward the semiconductor via-tunnelling. The NIOTs discharge time was modelled also taking into account the interface state density in a tunnelling relaxation model and it allowed us to locate traps within a tunnelling distance of up to 1.3 nm from the SiO/4H-SiC interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence of a non-abrupt (NA) SiO/4H-SiC interface. The NA interface shows the re-arrangement of the carbon atoms in a sub-stoichiometric SiO matrix. A mixed sp/sp carbon hybridization in the NA interface region suggests that the interfacial carbon atoms have lost their tetrahedral SiC coordination.

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

“…In particular, SCM in cross sections showed that the faceted 4H-SiC surface morphology incorporates a larger nitrogen amount compared to the basal planes, because it exposes different ratios between (0001) and (11−20) planes [47]. Other studies based on transmission electron microscopy (TEM) [52,53] and X-ray photoemission spectroscopy (XPS) [49] demonstrated that nitrogen is incorporated within a couple of 4H-SiC crystalline monolayers.…”

“…Many studies reported on the V th instability upon negative gate bias stress on MOSFETs [9, 52,70]. However, to get insights on the basic trapping mechanisms of NIOTs in the insulator, it is useful to analyse the behaviour of p-type MOS capacitors ( Figure 11) [71].…”

“…However, a clear identification and unification of the different processes is not yet provided. In order to gain deep insight into the chemical nature of the NIOTs responsible for the V th instability, and on the near SiO 2 /4H-SiC interface region, several microscopic chemical investigations have been presented in literature in the last decade [52,53,79,80]. The different results reported in literature are often due to the variety of SiO 2 /SiC interface processing.…”

“…Recently, Fiorenza et al [52] have reported on the presence of a narrow sub-stoichiometric SiO x layer produced on the re-oxidation of the 4H-SiC surface, even during nitridation (i.e., NO and N 2 O thermal treatments can move the SiO 2 /4H-SiC oxidation interface) of a deposited oxide layer. In particular, sub-Ångström resolution scanning transmission electron microscopy (STEM) analyses combined with electron energy loss spectroscopy (EELS) have been used to monitor the chemical environment of the first nanometer of insulator from the 4H-SiC interface.…”

“…In particular, sub-Ångström resolution scanning transmission electron microscopy (STEM) analyses combined with electron energy loss spectroscopy (EELS) have been used to monitor the chemical environment of the first nanometer of insulator from the 4H-SiC interface. Furthermore, the nano-chemical investigation was correlated with the time-dependent capacitance measurements and correlated with the NIOTs responsible for the MOSFET threshold voltage instability [52]. Figure 13a shows the cross-section of the SiO 2 /4H-SiC interface in high resolution dark field (DF) spectrum image that simultaneously collected all the elemental EELS maps.…”