Electroplating of Copper Conductive Layer on the Electroless-Plating Copper Seed Layer

Cho

Electrochem. Solid-State Lett.

et al. 2005

For application to Cu interconnection, superconformal electrodeposition has been performed on various substrates, including physical vapor deposited ͑PVD͒ Cu, two kinds of electroless deposited ͑ELD͒ Cu, TiN barrier, and metallorganic chemical vapor deposited Ru. ELD Cu with HCHO as the reducing agent was compatible with PVD Cu in terms of conformal characteristics and film continuity. Both PVD and ELD Cu seed layers enabled superconformal filling with distinct bumps. Superfilling was also attained on resistive substrates of TiN and Ru through Pd activation and subsequent slight seeding by electrodeposition to enhance the action of additives.

mentioning

confidence: 99%

Superconformal Cu Electrodeposition on Various Substrates

Cho

Electrochem. Solid-State Lett.

et al. 2005

“…7,8 Various deposition techniques such as sputtering, MOCVD, and layer-assisted deposition have been proposed for the preparation of this thin metal catalytic seed layer. [9][10][11][12] As we know, with the shrinkage in dimensions of interconnections it is getting more and more difficult to form a Cu seed layer with continuous step coverage on the sidewalls of fine holes and patterns. In a previous study, we examined the atomic layer deposition ͑ALD͒ of a Pd catalytic layer on various substrates.…”

mentioning

confidence: 99%

Atomic Layer Deposition of Pd on TaN for Cu Electroless Plating

Eyck

et al. 2005

J. Electrochem. Soc.

The essential points of this technique are the use of an ultrathin Pd catalyst on TaN by atomic layer deposition ͑ALD͒ and ultrasonic vibration in the electroless plating bath. We demonstrated Cu electroless deposition ͑ELD͒ on an ALD-Pd passivated TaN barrier layer. The Pd film deposited by ALD was 3 nm thickness on the TaN substrate and had good coverage with low surface roughness. For the Cu ELD process, we used ethylenediamine-tetraacetic acid ͑EDTA͒, glyoxylic acid, and additional chemicals such as polyethylene glycol, Re-610 and 2,2Јdipyridine. The Cu ELD was performed at a temperature of 60-65°C for 30 min. The success of ELD Cu in gap filling a patterned TaN substrate with 130 nm openings and an aspect ratio of three is attributed to the removal of hydrogen gas from the surface by ultrasonic vibration for 1 s after 15 min of deposition in the bath. In this work, we suggest the use of ultrasonic vibration in the Cu electroless plating bath without a chemical inhibitor.

“…[7][8][9] Moreover, the overall cost of the deposition process is * Electrochemical Society Active Member. z E-mail: domi@etri.re.kr; kwonkh@korea.ac.kr greatly increased when the high cost equipment is required for long processing.…”

mentioning

confidence: 99%

Metal∕Dielectric Liner Formation by a Simple Solution Process for through Silicon via Interconnection

Ham

Electrochem. Solid-State Lett.

Baek

et al. 2012

We investigated the formation of metal and dielectric liners in via holes. We obtained a conformal deposition of the Ag metal and PVPh liners in Si deep via holes. The measured Ag liner thickness increased from 0.18 μm to 1.44 μm as the radius of the via hole was increased from 0.85 μm to 5 μm. We also obtained a conformal deposition of the PVPh dielectric liner of about 830 nm in thickness in 10 μm deep via holes. The Ag metal and PVPh dielectric liners had uniform thickness on every region of their respective deep via holes.The emerging three-dimensional (3D) integration technology can form highly integrated systems by vertically stacking and connecting various materials, technologies and functional components. 1, 2 3D integration offers high interconnection density and the use of short wire lengths and small chips. At this time, through silicon via (TSV) is more attractive than other 3D interconnection methods because it offers a way to solve interconnection problems while providing integrated functions for higher performance of the integrated system. 3 The 3D TSV process in the front end of line process (FEOL) is divided into via etching, insulator and barrier deposition, seed layer deposition, metal filling and chemical mechanical polishing (CMP). 3 The conformal depositions of the insulator, barrier and seed layer are important for obtaining stable electrical isolation, uniform metal filling and high quality diffusion barrier.The formations of metal seed layer and metal liner in TSV process is performed by using the Cu metal source, because it is a low cost material. However, the Cu etching is very difficult process. Therefore, the patterning process of Cu is also very difficult task for electrical isolation. Meanwhile, Ag has recently attracted a great interest as a potential candidate for advanced ultra large scale integrated circuit (ULSI) metallization, due to the conductivity of Ag is about 7 percent higher than for Cu. Moreover, Ag is possible to pattering process for electrical isolation.To form the seed and barrier layers, sputtering or chemical vapor deposition (CVD) have been normally employed. 4, 5 Between the two methods, sputtering deposition is preferred over CVD deposition, because it is a more cost-effective process. However, sputter deposited films have very poor uniformity and stack-coverage inside via holes, especially inside high aspect ratios (ARs) via holes. 6,7 Meanwhile, the plasma-enhanced chemical vapor deposition (PECVD) method and the atmospheric-pressure CVD (APCVD) method are widely used for the formation of dielectric films. However, deposited dielectric layer have some problems, such as a low step coverage and high leakage current. On the other hand, the low-pressure CVD (LPCVD) method is used to form dielectric layers of highstep-coverage and low leakage current, but it requires a high process temperature. 8 Moreover, this method has difficulty in depositing thin dielectric layers uniformly in high ARs via holes because its process parameters must be controlled carefully.As ...