Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Abstract

For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were investigated with TCAD simulations. The self-heating effect (SHE) in a monolithic CFET is expected to be a critical problem given its highly compact architecture. DC analysis of the individual NFET and PFET devices revealed that increasing the channel width from 5.0 to 7.0 nm improved the thermal resistance up to 8.5% and the RC delay up to 9.6%, while greatly deteriorating the on/off ratio. AC CMOS inverter simulations of the CFET showed that reducing the NFET/PFET vertical separation from 30 to 10 nm resulted in 11.9% faster operation frequency and 3.4% reduced dynamic power loss, but 11.2% higher rise in device temperature. The clear trade-off relationships between the thermal and electrical performance factors necessitate optimization of the device dimension parameters. These findings are expected to provide critical insight for the design technology co-optimization (DTCO) in the 3-nm regime.INDEX TERMS Complementary FET (CFET), self-heating effect (SHE), 3D monolithic integration, TCAD, thermal resistance, time delay, figure of merit (FoM), CMOS inverter, device optimization.

Temperature rise effects on static characteristics of complementary FETs with Si and Ge nanosheets

“…Owing to the high device density, CFET-based ICs are concerned about the so-called selfheating effects of performance and reliability degradations due to heat generation. 6,7) Since the thermal conductivity of Ge is lower than that of Si, 8) it is predicted that Ge devices are less likely to release the generated heat and suffer from stronger self-heating effects. In fact, several experimental studies have confirmed this prediction.…”

Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

“…To further increase the on current, the researchers designed the FETs with different channel shapes [19] - [21]. The tree-shaped channel geometry has gained much attention in the semiconductor industry, especially among these channel shapes [22]- [24]. As shown in Fig.…”

“…The channel is constructed by linking the two nanosheets by an inter-bridge (IB), which is in the shape of a fin to form the Tree-shaped NS-FET. Without additional space, this inter-bridge provides an extra drive current for the vertically stacked MOSFETs [22]. However, in sub-10 nm devices, the space between the source and channel or the drain and channel is less and suffers from charge-sharing phenomena.…”