ELF-Murphy data on defects and test sets

McCluskey, E.J.; Al-Yamani, A.; Li, J.C.-M.; Tseng, Chao-Wen; Volkerink, E.; Ferhani, F.-F.; Li, E.; Mitra, Subhasish

doi:10.1109/vtest.2004.1299220

Cited by 46 publications

(12 citation statements)

References 30 publications

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“…Because of the many types of possible defects and the abstract nature of fault models, some defects will not be covered by, for example, a test with full stuck-at fault coverage. Defects that the test fails to cover are called test escapes [37,38,39,40]. To reduce test escape, different approaches exist, including the employment of a combination of more detailed fault models, application of a large (near exhaustive) test set, and N-detection.…”

Section: Fault Modellingmentioning

confidence: 99%

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

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Section: Fault Modellingmentioning

confidence: 99%

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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“…Screening all defective chips is extremely difficult and expensive for such large chips; achieving 99% stuck-at fault coverage for a ten million gate chip means there are 200,000 uncovered stuck-at faults. In deep submicron technology, there are many defects that cannot be detected with existing fault models [3]. Even if a test technique is able to screen 100% of defective chips, good chips may become defective before their expected life spans due to accidents such as power surge and human mistakes.…”

Section: Introductionmentioning

confidence: 99%

A self-diagnosis technique using Reed-Solomon codes for self-repairing chips

Tang¹,

Wang²

2009

2009 IEEE/IFIP International Conference on Dependable Systems &Amp; Networks

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A self-diagnosis circuit that can be used for builtin self-repair is proposed. The circuit under diagnosis is assumed to be comprised of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed first by the space compression circuit and then by the time compression circuit to reduce the volume of test response data. Both the space and the time compression circuit implement a Reed-Solomon code. Unlike prior work, in the proposed technique, responses of all FRUs are observed at the same time to reduce diagnosis time. The proposed diagnosis circuit can locate up to l defective FRUs. We propose a novel space-compression circuit that reduces hardware overhead by exploiting the frequency difference of the scan shift clock and the system clock. When the size of constituent multiple-input signature-register (MISR) is m, the total number of signatures to be stored for the fault-free signature is 2lmB bits, where 1 ≤ B ≤ m. The experimental results show that the proposed diagnosis circuit that can locate up to 4 defective FRUs in the same test session can be implemented with less than 1 % of hardware overhead for a large industrial design. Hardware overhead for the diagnosis circuit is lower for large CUDs.

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“…It was shown that test sets obtained for the IRF model are considerably smaller than the TDF test sets while providing the same coverage of finite resistance interconnect open defects. The second type of open defects which are detected by two-pattern tests are intra-gate opens, which are modeled by TSOP faults. In recent years several studies [13,14,15] have revealed that a considerable number of defective chips exhibit sequence dependent but timing independent (SDTI) failures. Such failures can be symptomatic of intra-gate opens of infinite resistance (TSOP faults).…”

Section: Introductionmentioning

confidence: 99%

Test Generation for Open Defects in CMOS Circuits

Devta-Prasanna

Gunda²,

Krishnamurthy³

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Open defects in CMOS circuits require two-pattern tests for detection. Traditionally, the only two-pattern tests included in manufacturing test are those targeting transition delay faults. Such tests, however, do not provide complete coverage of all the open defects. In this paper we propose the use of a unified test set that detects all inline resistance faults which model interconnect open defects and all transistor stuck-open faults which model intra-gate open defects in order to obtain a comprehensive coverage of open defects. We also describe a method of generating the proposed test set using an ATPG program for transition delay faults whose sizes are comparable to transition delay fault based test set.

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ELF-Murphy data on defects and test sets

Cited by 46 publications

References 30 publications

Investigation into voltage and process variation-aware manufacturing test

Investigation into voltage and process variation-aware manufacturing test

A self-diagnosis technique using Reed-Solomon codes for self-repairing chips

Test Generation for Open Defects in CMOS Circuits

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