Elimination of bond-pad damage through structural reinforcement of intermetal dielectrics

Saran, M.; Cox, R. G.; Martin, C. Wayne; Ryan, G. W.; Kudoh, Takeshi; Kanasugi, M.; Hortaleza, J.; Ibnabdeljalil, M.; Murtuza, Masood; Capistrano, D.; Roderos, R.; Macaraeg, R.

doi:10.1109/relphy.1998.670555

Cited by 27 publications

(15 citation statements)

References 1 publication

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“…Other than thermal stresses, considerable ''growth stress'' which is due to the grain growth is known to be developed for Cu interconnects formed by electroplating [5]. The stresses in the interconnects lead to stress-induced damages which is main reliability concerns in the Cu interconnects [6,7]. Furthermore, adoption of various low-k materials for dielectrics make a stressrelated problems more complicated.…”

Section: Introductionmentioning

confidence: 99%

Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects

Paik

Park

Joo

2004

Microelectronic Engineering

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Section: Introductionmentioning

confidence: 99%

Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects

Paik

Park

Joo

2004

Microelectronic Engineering

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“…The maximum stress in the model occurred at the outer edge of the bonded ball, in the dielectric in the uppermost layer. The predicted location maximum stress appears to be in agreement with a previous study of Al/low-k pad structures [4] where cracks in the dielectric layer below the bond pad were found to initiate near the edge of the bonded ball. The second failure mode evaluated by simulation is that in which the compressive stresses are high enough at the siliconto-contact interface that damage to the active device is possible, resulting in electrical failure.…”

Section: Simulations Of 5-metal Layer Boa Pad Structuressupporting

confidence: 89%

“…These evaluations focused on the incorporation of stress absorbing or dissipating layers below the bond pad to mitigate the forces applied to the pad during wirebonding. The placement of vias in the region under the pad for mechanical reinforcement was studied for Al/low-k interconnect structures [4]. This work examined only the mechanical response of the pad structures.…”

Section: Introductionmentioning

confidence: 99%

Reliability of bond over active pad structures for 0.13-μm CMOS technology

Hess

Downey²,

Halt³

et al.

53rd Electronic Components and Technology Conference, 2003. Proceedings.

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Advances in CMOS (Complementary Metal Oxide Semiconductor) device technology have helped reduce typical die core sizes by shrinking the minimum transistor feature size. In the case of wirebonded devices with high IO counts, the final die size is increasingly determined by the size and layout of the IO cells and corresponding wirebond pads. Typical wirebond pad designs consist of a top-level metal that does not include any circuitry beneath the bonding region. Further, placement rules typically require the placement of ESD circuitry, buffers, and busses inside of the bond pad ring in order to avoid possible damage and reliability failures caused by wirebonding. On die with high pad counts, this exclusion area can represent a significant percentage of the die area that is not used for circuitry.This papers describes a layout technology called Bond Over Active (BOA), that was developed to utilize this "excluded" region beneath wirebond pads in order to minimze die area. Two different BOA layouts are evaluated using a standard test structure. Wirebond assembly reliability and package stress reliability are determined. The transfer of forces from the top metal pad to the active silicon during wirebonding are predicted using mechanical simulations. The results of the simulations are used to explain the similar levels of reliability observed for the two BOA layouts.

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“…The low modulus of HSQ compared with traditional oxide dielectrics drove new integration strategies for fabricating robust devices and provided a strong foundation of experience upon which to begin integration with lower k and lower modulus dielectrics. An example of changes adopted for HSQ includes the implementation of metal trace cross hatching beneath bond pads to reinforce the stack beneath the pad and segment HSQ into smaller reservoirs [82]. This integration strategy completely eliminated the wirebond damage that was experienced during assembly learning cycles.…”

Section: A Adhesion Requirements For Assemblymentioning

confidence: 99%

Interface Reliability Assessments for Copper/Low-k Products

Hartfield

Ogawa

Park

et al. 2004

IEEE Trans. Device Mater. Relib.

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Multiple new materials are being adopted by the semiconductor industry at a rapid rate for both semiconductor devices and packages. These advances are driving significant investigation into the impact of these materials on device and package reliability. Active investigation is focused on the impact of back-end-of-line (BEOL) processing on Cu/low-k reliability. This paper discusses Cu/low-k BEOL interfacial reliability issues and relates key items from the assembly process and packaging viewpoint that should be managed in order to prevent adverse assembly impact on BEOL interfacial reliability. Reliability failure mechanisms discussed include interface diffusion-controlled events such as the well-known example of Cu electromigration (EM), as well as stress-migration voiding. Interface defectivity impact on dielectric breakdown and leakage is discussed. Lastly, assessments of assembly impact on these Cu/low-k interfacial concerns are highlighted.

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Elimination of bond-pad damage through structural reinforcement of intermetal dielectrics

Cited by 27 publications

References 1 publication

Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects

Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects

Reliability of bond over active pad structures for 0.13-μm CMOS technology

Interface Reliability Assessments for Copper/Low-k Products

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