Elucidation of the Density of States for Polycrystalline Silicon Vertical Thin-Film Transistors

Abstract

The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio I ON /I OFF of more than 10 6 and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method.

Four-terminal polycrystalline-silicon vertical thin-film transistors on glass substrates

“…In recent years, vertical (sidewall) TFTs (VTFTs) have attracted attention to resolve these issues. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] The channel length of planar TFTs is defined by the lithography process. Therefore, miniaturization is strongly affected by the lateral distortion and shrinkage of the glass substrate caused by heat treatment.…”