The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio I ON /I OFF of more than 10 6 and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method.

For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables to increase the driving current due to the reduction of the channel length, with the channel length only at the drain side. This lateral short channel TFT enables to increase the on-current when maintaining the field Accepted manuscript / Final version 2 effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 10 6 . The suppression of Schottky barrier at source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at source/drain sides and needs to be further optimized.

P and N type polycrystalline silicon has been applied in thin film transistors for driving all kinds of displays, and for building up CMOS-like circuits. For one aspect, the high driving current is required, which is usually achieved by improving field effect mobility of the active layer. For another aspect, balanced electrical characteristics are required for achieving CMOS-like logic circuits. In this article, in order to increase driving current, P and N type polycrystalline silicon vertical thin film transistors (TFTs) configuration is proposed that can get rid of the strict requirement of the field effect mobility in order to increase the driving current. In addition, the balanced electrical properties are demonstrated for P and N type vertical TFTs, which are elucidated by the density of states (DOS) calculations. The simple SPICE modelling indicates the potential application in CMOS inverter based on our vertical TFTs.