EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

Yoon, Insik; Chintaluri, Ashwin; Raychowdhury, Arijit

doi:10.1109/test.2016.7805834

Cited by 33 publications

(24 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2) BIST Techniques: BIST techniques presented in [80]- [82] were developed to perform in situ, statistical, retention failure testing of large STT-MRAM arrays.…”

Section: ) Test Generation Methodsmentioning

confidence: 99%

“…In order to alleviate the retention test time problem, Yoon et al [80], Yoon and Raychowdhury [81], and Hamdioui et al [82] proposed a new MBIST architecture that performs retention testing of large STT-MRAM arrays in a time-efficient manner. The proposed MBIST scheme reduces retention time considerably by: 1) applying weak write current to multiple rows in an array and 2) conducting a read operation only when a fault is detected within the rows under test.…”

Section: ) Test Generation Methodsmentioning

confidence: 99%

See 1 more Smart Citation

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

View full text Add to dashboard Cite

| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

show abstract

“…2) BIST Techniques: BIST techniques presented in [80]- [82] were developed to perform in situ, statistical, retention failure testing of large STT-MRAM arrays.…”

Section: ) Test Generation Methodsmentioning

confidence: 99%

Section: ) Test Generation Methodsmentioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

View full text Add to dashboard Cite

show abstract

“…Traditionally, a spot defect in an electronic circuit is modeled as a linear resistor, and the defect strength is represented by its resistance value [12,13,52]. For instance, missing material is modeled as a disconnection, while extra material is modeled as an undesired connection.…”

Section: Modeling Of Defects In Interconnects and Contactsmentioning

confidence: 99%

“…Conventionally, MTJ-related defects irrespective of their physical natures are modeled as linear resistors either in series with (i.e., OC t in Table 4) or in parallel (i.e., S1 BL-IN in Table 5) to an idea defect-free MTJ device, as can be found in [8][9][10][11][12][13]. Comparing the fault modeling results of our proposed pinhole defect model (PH) with the series resistor model OC t and the parallel resistor model S1 BL-IN reveals the following.…”

Section: Pinhole Defects In Mtj Devicesmentioning

confidence: 99%

“…Su et al [10] did intensive analysis of the excessive magnetic field during write operations and observed write disturbance faults; they validated those using chip measurements. Chintaluri et al [11,12] have taken the fault modeling one step further by studying the impact of resistive defects while considering extreme process variations; they proposed a test algorithm and its built-in-self-test (BIST) implementation. Recently, Nair et al [13] have reported detailed STT-MRAM fault analyses, based on injecting resistors into layout-aware netlist.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

View full text Add to dashboard Cite

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

show abstract

Radiation‐Tolerant Electronic Devices Using Wide Bandgap Semiconductors

Muhammad

Wang

Zhang

et al. 2022

Adv Materials Technologies

View full text Add to dashboard Cite

These energetic particles, such as electrons, protons, neutrons, X-rays, or gamma rays, induced damage in materials (used in electronic devices) through total ionization and displacement, [4] which would affect the reliability of the electronic devices. [5][6][7] Electronics failure occurs in harsh and inaccessible environments through various paths, such as electromagnetic waves, nuclear reactions, and high-frequency communications systems. Therefore, the radiationhardened requirements of the deployed electronic technology depend on the specific high-energy photons and particles in the radiation environment. For example, Mars exploration requires a special proton anti-radiation in electronics. At the same time, the safety supervision and inspection of the contaminated nuclear area are suggested to be equipped with high resilience towards the alpha, beta, and gamma rays. The development of radiation-hard electric circuits over the years has led researchers to consider the application of functional anti-irradiation material to devices. The current focus is on developing complementary metal-oxide semiconductors (CMOS) with wide bandgap semiconductors (WBGs), which are well suited to large-area aerospace applications. [8][9][10] As shown in Figure 1, a notable material class of WBGs can be listed as metal oxides (MOS), transition-metal dichalcogenides (TMDs), silicon carbide, gallium nitride, and others. WBGs materials contribute robust properties under harsh conditions due to their strong electronic compliance, high-temperature competence, and strong atomic bond energy. [11][12][13][14][15][16] They have been proposed as favorable materials for aerospace and other radiation-hardened applications. Generally, the bandgap in the semiconductor reflects the extra energy that a valence electron must access to become a free electron. Its large bandgap of more than 3 eV guarantees inherent reliability in the semiconductors, providing transparency for the low-energy photons. The large, spherical nsorbitals in the conduction band (CB) of MOS also play a critical role in high dopability for hosting a high density of electrons, leading to the remarkably tolerance to various radiation fluences. [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35] Understanding the apparent immunity of the WBGs to various radiation environments and radiation-hard electronic engineering would be critical for pushing the technology further and understanding its limitations. Efforts to address these issues have been underway over the past two decades. Substantial progress has also been made in designing radiation-hard thin films transistors (TFTs) with ZnO, Ga 2 O 3 , In 2 O 3 , SnO 2 , IGZO, SiC, GaN, and many other WBGs, The aspiration of electronic technologies that are resistant to high-energy cosmic radiation is essential for current harsh radiation environment exploration. Integrated circuits mostly require post-processing after designing, making their structures more complex than the standard systems. Thus, unique de...

show abstract

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

Cited by 33 publications

References 16 publications

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Defect and Fault Modeling Framework for STT-MRAM Testing

Radiation‐Tolerant Electronic Devices Using Wide Bandgap Semiconductors

Contact Info

Product

Resources

About