Enabling application-specific integrated circuits on limited pattern constructs

Morris, Daniel; Rovner, Vyacheslav; Pileggi, Larry; Strojwas, Andrzej J.; Vaidyanathan, Kaushik

doi:10.1109/vlsit.2010.5556202

Cited by 17 publications

(14 citation statements)

References 3 publications

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“…This topology has become possible in deeply scaled technology nodes due to the sub20nm regular pattern construct based IC design [10], [11]. LiM yields tremendous benefits at the system level mainly due to two attributes-proximity and flexibility.…”

Section: Logic In Memorymentioning

confidence: 99%

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory

Sadi

Akin

Popovici

et al. 2014

2014 IEEE High Performance Extreme Computing Conference (HPEC)

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Abstract-Real-time system level implementations of complex Synthetic Aperture Radar (SAR) image reconstruction algorithms have always been challenging due to their data intensive characteristics. In this paper, we propose a basis vector transform based novel algorithm to alleviate the data intensity and a 3D-stacked logic in memory based hardware accelerator as the implementation platform. Experimental results indicate that this proposed algorithm/hardware co-optimized system can achieve an accuracy of 91 dB PSNR compared to a reference algorithm implemented in Matlab and energy efficiency of 72 GFLOPS/W for a 8k×8k SAR image reconstruction.

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Section: Logic In Memorymentioning

confidence: 99%

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory

Sadi

Akin

Popovici

et al. 2014

2014 IEEE High Performance Extreme Computing Conference (HPEC)

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“…Recent studies of sub-20nm CMOS design indicate that memory and logic circuits can be implemented together using a small set of well-characterized pattern constructs [6,7]. Our early silicon experiments in a sub-20nm commercial SOI CMOS process demonstrate that this construct-based design enables logic and bitcells to be placed in a much closer proximity to each other without yield or hotspots pattern concerns.…”

Section: Introductionmentioning

confidence: 95%

“…But the use of commercial SRAM hardware IP is unable to incorporate application-specific customization that are required in the LiM design and also hinders comprehensive design space exploration. LiM physical synthesis is enabled by our smart memory synthesis framework, which is developed from the pattern construct based logic and memory co-design methodology [6,7]. Using this framework, embedded logic in the LiM is synthesized together with the memory cells to a small set of pre-characterized layout pattern constructs.…”

Section: Smart Memory Compilermentioning

confidence: 99%

A Smart Memory Accelerated Computed Tomography Parallel Backprojection

Zhu

Pileggi

Franchettis

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. As nanoscale lithography challenges mandate greater pattern regularity and commonality for logic and memory circuits, new opportunities are created to affordably synthesize more powerful smart memory blocks for specific applications. Leveraging the ability to embed logic inside the memory block boundary, we demonstrate the synthesis of smart memory architectures that exploits the inherent memory address patterns of the backprojection algorithm to enable efficient parallel image reconstruction at minimum hardware overhead. An end-to-end design framework in sub-20nm CMOS technologies was constructed for the physical synthesis of smart memories and evaluation of the huge design space. Our experimental results show that customizing memory for the computerized tomography (CT) parallel backprojection can achieve more than 30% area and power savings while offering significant performance improvements with marginal sacrifice of image accuracy.

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“…(8) shows that these eight pixels will be contained in the outputs of the above 1 x 8 access memory in most situations. Therefore, the memory architecture needs no change for the vertical parallel backprojection since we just take advantage of the unused memory outputs from the horizontal parallel backprojection.…”

Section: Hili I Iiiiimentioning

confidence: 99%

“…Recent studies of sub-20nm CMOS design indicate that memory and logic circuits can be implemented together using a small set of well-characterized pattern constructs [8], [9]. Our early silicon experiments in a commercial 14nm SOl CMOS process demonstrate that this construct-based design enables logic and bitcells to be placed in a much closer proximity to each other without yield or hotspots pattern con cerns.…”

Section: Introductionmentioning

confidence: 99%

Cost-effective smart memory implementation for parallel backprojection in computed tomography

Zhu¹,

Pileggi²,

Franchetti³

2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Abstract-As nanoscale lithography challenges mandate greater pattern regularity and commonality for logic and memory circuits, new opportunities are created to affordably synthesize more powerful smart memory blocks for specific applications.Leveraging the ability to embed logic inside the memory block boundary, we demonstrate the synthesis of smart memory archi tectures that exploits the inherent memory address patterns of the backprojection algorithm to enable efficient parallel image reconstruction at minimum hardware overhead. An end-to end design framework in sub-20nm CMOS technologies was constructed for the physical synthesis of smart memories and evaluation of the huge design space. Our experimental resultsshow that customizing memory for the computerized tomogra phy (CT) parallel backprojection can achieve more than 30% area and power savings while offering significant performance improvements with marginal sacrifice of image accuracy.

show abstract

Enabling application-specific integrated circuits on limited pattern constructs

Cited by 17 publications

References 3 publications

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory

A Smart Memory Accelerated Computed Tomography Parallel Backprojection

Cost-effective smart memory implementation for parallel backprojection in computed tomography

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