Enabling high-performance LPDDRx-compatible MRAM

Wang, Jue; Dong, Xiangyu; Xie, Yuan

doi:10.1145/2627369.2627610

Cited by 20 publications

(21 citation statements)

References 22 publications

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“…This is due to the operation sequence of STT-MRAM, which is different from DRAM, detailed in Section 2.4. Unlike DRAM, STT-MRAM has a non-destructive read which does not have to write-back; meaning it can issue precharge command sooner [24]. Hence, STT-MRAM tRC (Row cycle) for this configuration can be shorter than DRAM even with a longer tRCD and and tRP.…”

Section: Resultsmentioning

confidence: 99%

“…Whereas, being a non-volatile mem- ory, STT-MRAM read is non-destructive; i.e., it does not need to restore the data back to the array. Because of this, STT-MRAM can issue the consequent prechanrge command sooner [24]. Therefore, in specific cases, STT-MRAM tRC (Row cycle) can be shorter than DRAM even with a longer tRCD and and tRP.…”

Section: Timing Parameters: Our Proposalmentioning

confidence: 99%

“…A couple of studies [24][26] simulate STT-MRAM main memory by integrating publicly available STT-MRAM cell parameters into the CACTI [27] cache simulator. Using cache simulator to estimate timing and energy parameters of a main memory is not a straight-forward approach.…”

Section: Timing Parameters: Dead Endsmentioning

confidence: 99%

“…The authors also propose two STT-MRAM microarchitectual enhancements that would improve the STT-MRAM performance in the presence of the read disturbance errors. The proposal is evaluated based on the STT-MRAM parameters targeting LPDDR devices estimated by Wang et al [24] using CACTI [27] and NVSim [40].…”

Section: Stt-mram Opportunitiesmentioning

confidence: 99%

See 3 more Smart Citations

Enabling a reliable STT-MRAM main memory simulation

Asifuzzaman

Verdejo

Radojković

2017

Proceedings of the International Symposium on Memory Systems

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STT-MRAM is a promising new memory technology with very desirable set of properties such as non-volatility, byteaddressability and high endurance. It has the potential to become the universal memory that could be incorporated to all levels of memory hierarchy. Although STT-MRAM technology got significant attention of various major memory manufacturers, to this day, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing parameters which are required to perform a cycle accurate main memory simulation. Our study presents a detailed analysis of STT-MRAM main memory timing and propose an approach to perform a reliable system level simulation of the memory technology. We seamlessly incorporate STT-MRAM timing parameters into DRAMSim2 memory simulator and use it as a part of the simulation infrastructure of the high-performance computing (HPC) systems. Our results suggests that, STT-MRAM main memory would provide performance comparable to DRAM, while opening up various opportunities for HPC system improvements. Most importantly, our study enables researchers to conduct reliable system level research on STT-MRAM main memory, and to explore the opportunities that this technology has to offer.

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Section: Resultsmentioning

confidence: 99%

Section: Timing Parameters: Our Proposalmentioning

confidence: 99%

Section: Timing Parameters: Dead Endsmentioning

confidence: 99%

Section: Stt-mram Opportunitiesmentioning

confidence: 99%

See 2 more Smart Citations

Enabling a reliable STT-MRAM main memory simulation

Asifuzzaman

Verdejo

Radojković

2017

Proceedings of the International Symposium on Memory Systems

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Section: Related Workmentioning

confidence: 99%

STT-MRAM for real-time embedded systems

Asifuzzaman

Fernandez

Radojković

et al. 2019

Proceedings of the International Symposium on Memory Systems

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STT-MRAM is an emerging non-volatile memory quickly approaching DRAM in terms of capacity, frequency and device size. Intensified efforts in STT-MRAM research by the memory manufacturers may indicate a revolution with STT-MRAM memory technology is imminent, and therefore it is essential to perform system level research to explore use-cases and identify computing domains that could benefit from this technology. Special STT-MRAM features such as intrinsic radiation hardness, non-volatility, zero stand-by power and capability to function in extreme temperatures makes it particularly suitable for aerospace, avionics and automotive applications. Such applications often have real-time requirementsthat is, certain tasks must complete within a strict deadline. Analyzing whether this deadline is met requires Worst Case Execution Time (WCET) Analysis, which is a fundamental part of evaluating any real-time system. In this study, we investigate the feasibility of using STT-MRAM in real-time embedded systems by analyzing average system performance impact and WCET implications. CCS CONCEPTS • Computer systems organization → Processors and memory architectures; Embedded systems; • Hardware → Non-volatile memory; • Computing methodologies → Real-time simulation;

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