Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology

Franca-Neto, L.M.; Pardy, Patrick; Ly, M.P.; Rangel, Ryan M. Dias; Suthar, Sailesh; Syed, T.; Bloechel, B.; Lee, S.; Burnett, Chris; Cho, D.; Kau, D.; Fazio, A.; Soumyanath, K.

doi:10.1109/vlsic.2002.1015074

Cited by 26 publications

(8 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…as well as by digital circuit repetition and clock frequencies. One study also showed that low frequency substrate noise is mainly caused by random digital logic activity [14]. The conclusion from this is that substrate noise can be strong in certain frequency bands and weaker in others.…”

Section: Substrate Noise Measurementsmentioning

confidence: 97%

See 1 more Smart Citation

Study of substrate noise and techniques for minimization

Peng

Lee

2004

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

This thesis presents a study of the effects of substrate noise on analog circuits in mixedsignal chips and techniques for minimizing these harmful effects on sensitive analog circuits. A microchip built in a 0.25um CMOS epitaxial process was designed, fabricated, and tested for this research.Through the use of an on-chip sampling scope, the effect of substrate noise generated by digital inverters with coupling capacitors to the substrate on analog circuits was characterized. Substrate noise coupled into a representative analog circuit, a switched capacitor delta-sigma modulator primarily through the asymmetrical parasitics of the input sampling circuit. Furthermore, since some of the parasitics are nonlinear with input voltage, substrate noise couples into the analog circuits producing an input signal dependent component and an input signal independent component. The substrate noise, with decay time constants of a few nanoseconds and ringing frequencies of few hundred megahertz, can decrease analog circuit performance. In the case of a delta-sigma modulator, substrate noise caused the signal to noise power ratio to decrease by more than 18dB, 3 bits in terms of analog-to-digital converter metrics.In addition, two techniques of minimizing the substrate noise and its effects were explored. The first used a replica delta-sigma modulator on the same chip to subtract the effects of substrate noise from the original delta-sigma modulator. This method proved useful for removing input signal independent substrate noise, but not input signal dependent substrate noise which dominates in-band noise for large input signal magnitudes.The second technique involved an active substrate noise cancellation system. A discrete time feedback loop senses the substrate noise, processes it through a filter, and uses an array of digital inverters to cancel the substrate noise. The principal advantages of this technique are the shaping of substrate noise through a designed filter without a significant power penalty and design independence from the analog and digital components. Measured data shows that this technique is capable of over 20dB reduction in substrate noise on the substrate voltage itself. Measured data also shows over 10dB improvement in SNDR of the delta-sigma modulator in certain cases.

show abstract

Section: Substrate Noise Measurementsmentioning

confidence: 97%

“…Substrate noise generated by digital circuits has been measured and characterized in many different ways for many different fabrication technologies and circuit applications [4] [14]. In general, the data shows that substrate noise waveforms tend to ring in response to events such as switching digital gates.…”

Section: Substrate Noise Measurementsmentioning

confidence: 99%

Study of substrate noise and techniques for minimization

Peng

Lee

2004

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…The deep N-well (DNW) can be respectively added to each group for decreasing substrate noise coupling [6]. The DNW isolates the P-well, which is the noise source and P substrate with each other.…”

Section: ) Double Deep N-well Isolation Structurementioning

confidence: 99%

An Implementation of Integral Low Power Techniques for Modern Cell-Based VLSI Designs

Aswath¹,

Puttaraju²,

Kalpana³

2011

IJCEE

View full text Add to dashboard Cite

Abstract-Recent research has proposed several low-power design techniques for VLSI circuitry in nano-scale CMOS era. However, these techniques always involve custom layout design or novel Electronic Design Automation (EDA) flows. In this paper essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place and route (P&R) tools. These techniques enable the possibility to integrated low power techniques into standard Cell-Based physical design flow. The result of these research shows a little overhead in design procedure equally area overhead compare with fully custom design flow. The proposed low power design techniques can be cooperated with modern power management system to enable the power reduction in targeting circuitry with small implementation overheads.Index Terms-Cell-Based, Low-power, Nano-scale, physical design, Place and route.

show abstract

“…The noise power with 10-dB noise figure and 1056-MHz channel bandwidth is Ϫ73. 8 To achieve an error-free operation of the receiver at BER ϭ 10 Ϫ4 , the substrate coupling noise power due to a fringing field effect between the Tx and Rx is presented as…”

Section: Analysis Of Near-field Emimentioning

confidence: 99%

Interdevice isolation characteristics for design and fabrication of 60‐GHz WPAN SoCs

Kim

Lee

Yun

et al. 2008

Micro & Optical Tech Letters

View full text Add to dashboard Cite

them can still be observed, which can be attributed to the unexpected tolerance of fabrication. CONCLUSIONA novel dual-frequency unequal Wilkinson power divider is presented in this article, which fulfills an arbitrary unequal power split and all the other features of a conventional Wilkinson unequal power divider simultaneously at two arbitrary frequencies. The structure of this power divider and the formulas to determine its parameters have been given and a good agreement between the simulation and measurement has been achieved. This simple topology and design procedure make the proposed circuit suitable for dual-frequency applications, which are more demanding at near future. REFERENCES 1. ABSTRACT: The high interdevice isolation levels is one of the key technologies in the design and fabrication of 60-GHz WPAN SoC. To obtain proper interdevice isolation levels, we have analyzed and measured substrate coupling effects with various isolation techniques like a trench and implant structure.From the analyzed and measured results, the feasibility of the implant has confirmed to be applicable to the mm-wave SoC, and also derived an equivalent circuit form these results, which can be helpful to the design and fabrication of the 60-GHz WPAN SoC. ABSTRACT:We propose a simple configuration of a traveling wave tunable semiconductor fiber ring laser. The proposed laser can be tuned over 93 nm with an output power of 1.3 dBm using a thin film fiber Fabry Pérot filter. Figure 4The measured results and equivalent circuit results of (a) the magnitude and (b) phase of the interdevice isolation levels 1702

show abstract

Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology

Cited by 26 publications

References 1 publication

Study of substrate noise and techniques for minimization

Study of substrate noise and techniques for minimization

An Implementation of Integral Low Power Techniques for Modern Cell-Based VLSI Designs

Interdevice isolation characteristics for design and fabrication of 60‐GHz WPAN SoCs

Contact Info

Product

Resources

About