Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning

Glokler, T.; Baumgartner, Jason; Shanmugam, D.; Seigler, R.; Huben, G. Van; Ramanandray, B.; Mony, Hari; Roessler, Peter

doi:10.1109/fmcad.2006.12

Cited by 8 publications

(4 citation statements)

References 9 publications

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“…Various strategies may be used to decide when to terminate BMC: an upper-bound on BMC depth or runtime can be used. In our framework, we prefer increasing BMC depth until there is no change in the localized netlist for n consecutive steps (lines [17][18]. The value of n can be varied to increase confidence in the abstracted model such that it is immune to spurious counterexamples.…”

Section: A Generating Support Bitvectorsmentioning

confidence: 99%

“…This debug bus logic monitors a configurable set of internal signals in real-time, non-intrusively while the chip is functionally running. Debug bus verification entails a large number of properties (often one per monitor point), within very large design components -sometimes entire chips [17]. Localization is the dominant method to verify debug bus designs as they often contain >10M gates [17].…”

Section: B Proprietary Designsmentioning

confidence: 99%

“…Debug bus verification entails a large number of properties (often one per monitor point), within very large design components -sometimes entire chips [17]. Localization is the dominant method to verify debug bus designs as they often contain >10M gates [17]. Note that concurrent verification of all properties is completely intractable.…”

Section: B Proprietary Designsmentioning

confidence: 99%

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Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties

Dureja

Baumgartner

Ivrii

et al. 2019

2019 Formal Methods in Computer Aided Design (FMCAD)

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From equivalence checking to functional verification to design-space exploration, industrial verification tasks entail checking a large number of properties on the same design. State-of-the-art tools typically solve all properties concurrently, or one-at-a-time. They do not optimally exploit subproblem sharing between properties, leaving an opportunity to save considerable verification resource via concurrent verification of properties with nearly identical cone of influence (COI). These high-affinity properties can be concurrently solved; the verification effort expended for one can be directly reused to accelerate the verification of the others, without hurting per-property verification resources through bloating COI size. We present a near-linear runtime algorithm for partitioning properties into provably high-affinity groups for concurrent solution. We also present an effective method to partition high-structural-affinity groups using semantic feedback, to yield an optimal multi-property localization abstraction solution. Experiments demonstrate substantial end-to-end verification speedups through these techniques, leveraging parallel solution of individual groups.

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Section: A Generating Support Bitvectorsmentioning

confidence: 99%

Section: B Proprietary Designsmentioning

confidence: 99%

Section: B Proprietary Designsmentioning

confidence: 99%

See 1 more Smart Citation

Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties

Dureja

Baumgartner

Ivrii

et al. 2019

2019 Formal Methods in Computer Aided Design (FMCAD)

Self Cite

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“…Abramovici et al [1] propose a different reconfigurable architecture, also with the goal of providing efficient signal access for debugging. Also, many companies have their own, in-house access mechanisms to help in debugging (e.g., [7]), but published details are sparse. Nevertheless, the sort of on-chip access we assume are clearly very realistic.…”

Section: A Related Workmentioning

confidence: 99%

BackSpace: Formal Analysis for Post-Silicon Debug

Paula

Gort

et al. 2008

2008 Formal Methods in Computer-Aided Design

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Abstract-Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse. We introduce a new paradigm for using formal analysis, augmented with some on-chip hardware support, to automatically compute error traces that lead to an observed buggy state, thereby greatly simplifying the post-silicon debug problem. Our preliminary simulation experiments demonstrate the potential of our approach: we can "backspace" hundreds of cycles from randomly selected states of some sample designs. Our preliminary architectural studies propose some possible implementations and show that the on-chip overhead can be reasonable. We conclude by surveying future research directions.

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Word-Level Sequential Memory Abstraction for Model Checking

Bjesse

2008

2008 Formal Methods in Computer-Aided Design

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Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning

Cited by 8 publications

References 9 publications

Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties

Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties

BackSpace: Formal Analysis for Post-Silicon Debug

Word-Level Sequential Memory Abstraction for Model Checking

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