BackSpace: Formal Analysis for Post-Silicon Debug

Paula, Flavio M. De; Gort, Marcel; Hu, Alan J.; Wilton, Steven J. E.; Yang, Jin

doi:10.1109/fmcad.2008.ecp.9

Cited by 60 publications

(37 citation statements)

References 45 publications

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“…More recently, SAT-based methodologies are shown to exhibit significant performance advantages when compared to traditional techniques [15]. Following the original work, extensions using Quantified Boolean Formula (QBF) [19], maximum satisfiability [16], UNSAT cores [24] and others [25], [26] extend the benefits of the original methodology. With no loss of generality, this paper presents BMD in terms of SAT-based debugging.…”

Section: B Sat-based Design Debuggingmentioning

confidence: 99%

Bounded Model Debugging

Keng

Safarpour

Veneris

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical design blocks exceeding half a million synthesized logic gates and error traces in the thousands of clock cycles, the complexity of the debugging problem poses a great challenge to automated debugging techniques. This work aims to address this daunting challenge by introducing the Bounded Model Debugging methodology that iteratively analyzes bounded sequences of the error trace. Two techniques are introduced in this methodology to solve this growing problem. The first technique iteratively analyzes bounded subsequences of the error trace of increasing size until the error is found or the entire trace is analyzed. The second technique partitions the error trace into non-overlapping bounded sequences of clock cycles which are each separately analyzed. A discussion of these two techniques is presented and a unified methodology that leverages the strengths of both techniques is developed. Empirical results on real industrial designs show that for large designs and long error traces the proposed methodology can find the actual error in 79% of cases with the first technique and 100% of cases with the second technique. In cases where the methodology is not used only 21% of cases are able to find the actual error. These numbers confirm the benefits of the proposed methodology to allow conventional automated debuggers to handle much larger real-life circuits.

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Section: B Sat-based Design Debuggingmentioning

confidence: 99%

Bounded Model Debugging

Keng

Safarpour

Veneris

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Some of these work focus on improving observability and traceability of hardware at the post-silicon stage. A notable work is "backspace" [6], it uses SAT-solving techniques to provide an execution trace to a crashed post-silicon state, thus facilitating off-line debugging. Several approaches [3,8,12] integrate formal specifications into post-silicon checking of hardware by observing its execution trace.…”

Section: Related Workmentioning

confidence: 99%

Post-silicon conformance checking with virtual prototypes

Xie

Cong

2013

Proceedings of the 50th Annual Design Automation Conference

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Virtual prototypes are increasingly used in device/driver co-development and co-validation to enable early driver development and reduce product time-to-market. However, drivers developed over virtual prototypes often do not work readily on silicon devices, since silicon devices often do not conform to virtual prototypes. Therefore, it is important to detect the inconsistences between silicon devices and virtual prototypes.We present an approach to post-silicon conformance checking of a hardware device with its virtual prototype, i.e., a virtual device. The conformance between the silicon and virtual devices is defined over their interface states. This approach symbolically executes the virtual device with the same driver request sequence to the silicon device, and checks if the interface states of the silicon and virtual devices are consistent. Inconsistencies detected indicate potential errors in either the silicon device or the virtual device. We have evaluated our approach on three network adapters and their virtual devices, and found 15 inconsistencies exposing 15 real bugs in total from the silicon and virtual devices. The results demonstrate that our approach is useful and efficient in facilitating device/driver covalidation at the post-silicon stage.

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“…The BackSpace framework presented in [25] aims to provide the ability to trace back thousands of cycles from the crash state to determine the original error excitation state. It works by augmenting the design with hardware to record small signatures of key states.…”

Section: B Techniques For Debugging Silicon Prototypesmentioning

confidence: 99%

From RTL to silicon: The case for automated debug

Veneris

Keng

Safarpour

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Abstract-Computer-aided design tools are continuously improving their scalability and efficiency to mitigate the high cost associated with designing and fabricating modern VLSI systems. A key step in the design process is the root-cause analysis of detected errors. Debugging may take months to close, introduce high cost and uncertainty ultimately jeopardizing the chip release date. This study makes the case for debug automation in each part of the design flow (RTL to silicon) to bridge the gap. Contemporary research, challenges and future directions motivate for the urgent need in automation to relieve the pain from this highly manual task.

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BackSpace: Formal Analysis for Post-Silicon Debug

Cited by 60 publications

References 45 publications

Bounded Model Debugging

Bounded Model Debugging

Post-silicon conformance checking with virtual prototypes

From RTL to silicon: The case for automated debug

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