Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

“…The FeFETs reported in the literature exhibited a small MW (≈3 V) and limited endurance (≈10 5 cycles) characteristics, making these devices unsuitable for PIM applications. ,,− ,− These limitations result from the capacitance mismatch between the low capacitance of the MOSFET ( C MOS ) and the high capacitance of the ferroelectrics ( C FE ) in the gate stack (Figure S7). To circumvent this, we employed the MFMIS gate structure.…”

“…In the mainstream research on PIM applications, various current-domain computing-based PIM has been demonstrated. ,,,, However, the high-energy consumption of the DC current in MAC operation is a critical barrier to PIM applications. In comparison, charge-domain computing-based PIM consumes only dynamic energy; therefore, it provides low energy consumption. ,,, Among them, the local multiply and global accumulate (LM-GA) array is of great interest because of its energy-efficient accumulation operation via charge-domain computing . However, because the drain of the FeFET cannot be controlled by a column-wise control signal, the LM-GA array has a definite limitation regarding the parallel update of multiple weights, which is practical for PIM applications.…”

“…Over the past 5 decades, computing science and technology based on the von Neumann architecture have provided outstanding advances in every field. − However, with the development of artificial intelligence (AI) processors, modern computing systems require intensive computations and a large memory capacity. , AI processors typically use convolutional neural networks (CNN) comprising several convolution and fully connected (FC) layers. In particular, the convolution and FC layers require parallel multiply-and-accumulation (MAC) operations, requiring intensive data movement. − However, in the von Neumann architecture, a large latency and energy consumption exist owing to the frequent data movement between the central processing unit and memory. − , In this regard, processing-in-memory (PIM) has been introduced as a promising approach. − ,− Inspired by the neural network of the human brain, the PIM architecture reduces the latency and energy consumption in data movement by allowing highly parallel computing in the memory module (Figure a).…”

“…Current-domain computing suffers from energy consumption by DC currents and is vulnerable to process–voltage–temperature (PVT) variations. In contrast, charge-domain computing provides low energy consumption because it consumes only dynamic energy and exhibits high immunity to PVT variation by capacitor-based charge sharing, which has lower variations than transistor currents. , Therefore, NVM and charge-domain computing-based PIM are valuable for energy-efficient and reliable architectures.…”

Computing-in-memory with thin-filmtransistors: challenges and opportunities

“…Charge-domain CiM (CD-CiM) is such a method that uses capacitors for analog accumulation operation and transistors for digital-style switch operations. It has been successfully verified for low sensitivity to transistor nonidealities in CMOS [36][37][38] and beyond-CMOS technologies [86]. The principle of CD-CiM is based on the charge redistribution among the capacitor array, which averages the voltages applied to the separate plates of each capacitor as shown in figure 10(a).…”