Encapsulated double-bump WL-CSP: design and reliability

Abstract

A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 x 8 array of bumps on a 5 x 5 mm 2 die. Micro Moiré Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported. IntroductionWafer-Level packaging is becoming a very popular method of packaging low to mid-I/O devices for several reasons: cost, size, and ease of testing. Cost is the largest force driving wafer-level packaging.Using batch processing, an entire wafer can be packaged instead of packaging each singulated die. Wafer level packaging reduces packaging steps, eliminates the use of underfill, and allows for centralized processing in the fab. Also, packaging the wafer allows for a high degree of process integration due to the use of fab-type processing such as thin films and lithography which decreases cost. Centralized packaging in the fab also reduces packaging time and inventory, since devices no longer have to be packaged separately between the fab and the assembly houses. Size is also a driving force for wafer-level packaging. The footprint of a WL-CSP is the same as the die. Wafer-level burn-in and test (WLBT) is also driving the industry toward WL-CSP solutions. Test will no longer be necessary before packaging. A completely packaged wafer can be burned-in and tested after the final packaging step resulting in known good packages (KGP). Testing at the wafer level can reduce test costs by as much as 50%, requires less test capital, and reduces the number of test steps.

Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing

“…Although a large number of studies have been done on WL-CSP [3] [4], it is difficult to apply WL-CSP to topography wafer, such as MEMS and stacked ICs. The main reason is that it makes it difficult to apply photolithography process to make traces, vias, and ball grid array (BGA) lands.…”

Reliability enhancement of wafer level packages with nano-column-like hollow solder ball structures

“…It is generally conceived that the high compliance of polymer film (e.g., low Young's modulus) results in solder joint stress reduction [10]. Ball shape, geometry, standoff height, and material also play an important role in thermo-mechanical performance of WLPs [11][12][13][14][15][16]. Previous works have demonstrated that a greater standoff height with a slim ballshape offer improved reliability performance.…”

Development on wafer level anisotropic conductive film for flip-chip interconnection

“…Major developments on WLP are being performed on wafer bumping and different solutions and confip-ations are proposed by companies and laboratories [3,4,5]. The aim is to reduce the connection stress and achieve good reliability without having to perform individual underfill after Flip-Chip hybridization on board which is a costly operation.…”