Anisotropic Conductive Film (ACF) consists of an adhesive polymer matrix with dispersed conductive particles. In Flip-Chip technology, ACF has been used in place of solder and underfill for chip attachment to glass or organic substrates. The filler particles establish the electrical contacts between the interconnecting areas. ACF Flip-Chip bonding provides finer pitch, higher package density, reduced package size and improved lead-free compatibility. Nevertheless, the interconnection is different from traditional solder joints, the integrity and durability of the ACF interconnects have major concerns. Failures in Anisotropic Conductive Film (ACF) parts have been reported after temperature cycling, moisture preconditioning and autoclave. The failures have not been well understood and have been attributed to a wide variety of causes. This paper investigates the failure mechanism of ACF using finite element simulation. From a failure-initiation point of view, the response of ACF packages to environmental (temperature and humidity) exposure is very different from standard underfilled packages. These differences cause the ACF package to fail in different ways from an underfilled package. Simulation results have shown that moisture-induced ACF swelling and delamination is the major cause of ACF failure. With moisture absorption, the loading condition at the interface is tensile-dominant, which corresponds to lower interface toughness (or fracture resistance). This condition is more prone to interface delamination. Therefore, the reliability of ACF packages is highly dependent on the ACF materials. The paper suggests a new approach towards material selection for reliable ACF packages. This approach has very good correlation with experimental results and reliability testing of various ACF materials.

Anisotropic conductive film (ACF) consists of an adhesive polymer matrix with dispersed conductive particles. In flip-chip technology, ACF has been used in place of solder and underfill for chip attachment to glass or organic substrates. The filler particles establish the electrical contacts between the interconnecting areas. ACF flip-chip bonding provides finer pitch, higher package density, reduced package size and improved lead-free compatibility. Nevertheless, the interconnection is different from traditional solder joints, the integrity and durability of the ACF interconnects have major concerns.Failures in anisotropic conductive film (ACF) parts have been reported after temperature cycling, moisture preconditioning and autoclave. The failures have not been well understood and have been attributed to a wide variety of causes. This paper investigates the failure mechanism of ACF using finite element simulation. From a failure-initiation point of view, the response of ACF packages to environmental (temperature and humidity) exposure is very different from standard underfilled packages. These differences cause the ACF package to fail in different ways from an underfilled package.Simulation results have shown that moisture-induced ACF swelling and delamination is the major cause of ACF failure. With moisture absorption, the loading condition at the interface is tensile-dominant, which corresponds to lower interface toughness (or fracture resistance). This condition is more prone to interface delamination. Therefore, the reliability of ACF packages is highly dependent on the ACF materials. The paper suggests a new approach toward material selection for reliable ACF packages. This approach has very good correlation with experimental results and reliability testing of various ACF materials.

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A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 x 8 array of bumps on a 5 x 5 mm 2 die. Micro Moiré Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported. IntroductionWafer-Level packaging is becoming a very popular method of packaging low to mid-I/O devices for several reasons: cost, size, and ease of testing. Cost is the largest force driving wafer-level packaging.Using batch processing, an entire wafer can be packaged instead of packaging each singulated die. Wafer level packaging reduces packaging steps, eliminates the use of underfill, and allows for centralized processing in the fab. Also, packaging the wafer allows for a high degree of process integration due to the use of fab-type processing such as thin films and lithography which decreases cost. Centralized packaging in the fab also reduces packaging time and inventory, since devices no longer have to be packaged separately between the fab and the assembly houses. Size is also a driving force for wafer-level packaging. The footprint of a WL-CSP is the same as the die. Wafer-level burn-in and test (WLBT) is also driving the industry toward WL-CSP solutions. Test will no longer be necessary before packaging. A completely packaged wafer can be burned-in and tested after the final packaging step resulting in known good packages (KGP). Testing at the wafer level can reduce test costs by as much as 50%, requires less test capital, and reduces the number of test steps.

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