Copper films of different thicknesses of 0.2, 0.5, 1 and 2 microns were electroplated on top of the adhesion-promoting barrier layers on <100> single crystal silicon wafers. Controlled Cu grain growth was achieved by annealing films in vacuum.The Cu film microstructure was characterized using Atomic Force Microscopy and Focused Ion Beam Microscopy. Elastic modulus of 110 to 130 GPa and hardness of 1 to 1.6 GPa were measured using the continuous stiffness option (CSM) of the Nanoindenter XP. Thicker films appeared to be softer in terms of the lower modulus and hardness, exhibiting a classical Hall-Petch relationship between the yield stress and grain size. Lower elastic modulus of thicker films is due to the higher porosity and partially due to the surface roughness. Comparison between the mechanical properties of films on the substrates obtained by nanoindentation and tensile tests of the freestanding Cu films is made.

As industry trends drive increased integration and speed, Cuilow-k structures are the desired choice for advanced IC circuits. A simulation methodology has been developed to study the flip-chip packaging effect on the Cullow-k structures. Multi-level submodeling techniques have heen used to bridge the scale difference between the flip-chip packages and the metalidielectric stacks. Interface fracture mechanics-based approach is used to determine the crack driving force at each interface. The impact of the die-attach process on interconnect reliability has been evaluated.To achieve smaller feature size and higher speed in future chips, we can replace Si02 with low-k dielectric material in all via and trench layers, or increase the number of metal layers. This paper evaluates the effect of placing low-k as last metal dielectric and low-k at all via and trench layers, as well as the effect of eight-layer metal/dielectric stack compared with the four-layer metal stack.The future flip-chip Cuilow-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provided a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flipchip packages.

No abstract

No abstract

Anisotropic Conductive Film (ACF) consists of an adhesive polymer matrix with dispersed conductive particles. In Flip-Chip technology, ACF has been used in place of solder and underfill for chip attachment to glass or organic substrates. The filler particles establish the electrical contacts between the interconnecting areas. ACF Flip-Chip bonding provides finer pitch, higher package density, reduced package size and improved lead-free compatibility. Nevertheless, the interconnection is different from traditional solder joints, the integrity and durability of the ACF interconnects have major concerns. Failures in Anisotropic Conductive Film (ACF) parts have been reported after temperature cycling, moisture preconditioning and autoclave. The failures have not been well understood and have been attributed to a wide variety of causes. This paper investigates the failure mechanism of ACF using finite element simulation. From a failure-initiation point of view, the response of ACF packages to environmental (temperature and humidity) exposure is very different from standard underfilled packages. These differences cause the ACF package to fail in different ways from an underfilled package. Simulation results have shown that moisture-induced ACF swelling and delamination is the major cause of ACF failure. With moisture absorption, the loading condition at the interface is tensile-dominant, which corresponds to lower interface toughness (or fracture resistance). This condition is more prone to interface delamination. Therefore, the reliability of ACF packages is highly dependent on the ACF materials. The paper suggests a new approach towards material selection for reliable ACF packages. This approach has very good correlation with experimental results and reliability testing of various ACF materials.