2015
DOI: 10.1109/temc.2015.2427362
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Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

Abstract: This paper proposes a novel approach to evaluate design alternatives for high-speed links on printed circuit boards. The approach combines evaluations of signal integrity and link input power. For a comprehensive analysis, different link designs are made comparable through the application of identical constraints, with the link input power as the single figure of merit for a systematic, quantitative comparison of design alternatives. The analysis relies upon a combination of efficient physics-based via and tra… Show more

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Cited by 16 publications
(12 citation statements)
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“…increasing performance requirements within the PCB industry, such as larger aspect ratio, driven by a demand for a higher number of electronic components and stacking densities of PCB layer. The technological growth of high-value PCBs is currently driven by the development of boards which can propagate high frequency signals above 1 GHz (Okubo et al, 2013) with transmission speeds over 25 Gb/s (Muller et al, 2015) and at low bit error rates. Additionally, small track feature sizes are desired to allow for large board component densities.…”
mentioning
confidence: 99%
“…increasing performance requirements within the PCB industry, such as larger aspect ratio, driven by a demand for a higher number of electronic components and stacking densities of PCB layer. The technological growth of high-value PCBs is currently driven by the development of boards which can propagate high frequency signals above 1 GHz (Okubo et al, 2013) with transmission speeds over 25 Gb/s (Muller et al, 2015) and at low bit error rates. Additionally, small track feature sizes are desired to allow for large board component densities.…”
mentioning
confidence: 99%
“…In such cases, the trace time delay can be easily greater than that of the gate circuits for high density and high speed on chip circuits. The crosstalk noise among traces and circuits has become an unavoidable bottleneck in signal integrity design [4][5][6][7]. To overcome the limitation of global trace interconnection and to solve signal integrity issues in ultralarge-scale integrated circuits (ULSICs), such as system-on-chip (SoC) or network-on-chip (NoC), the on-chip antenna-based wireless interconnection method has been developed [8][9][10][11][12][13][14][15][16].…”
Section: Introductionmentioning
confidence: 99%
“…In addition, the parasitic effects degrade undeniably the PCB performances . It was predicted that this high‐density configuration requires a consideration of the signal integrity and power integrity effects . Therefore, optimization techniques have been proposed to improve the signal transmission link .…”
Section: Introductionmentioning
confidence: 99%
“…15 It was predicted that this high-density configuration requires a consideration of the signal integrity and power integrity effects. [16][17][18][19] Therefore, optimization techniques have been proposed to improve the signal transmission link. 20,21 More accurate circuit modeling 22,23 and characterization techniques 24 are introduced.…”
Section: Introductionmentioning
confidence: 99%