Energy-aware writes to non-volatile main memory

Chen, Jie; Chiang, Ron C.; Huang, H. Howie; Venkataramani, Guru

doi:10.1145/2094091.2094104

Cited by 36 publications

(23 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…One solution to eliminating redundant writes completely is comparing every bit before a write and updating only changed bits [Zhou et al 2009;Chen et al 2011a]. It is implemented by adding an XNOR gate to compare new data with old data when writing.…”

Section: Reducing Wear On Pcmmentioning

confidence: 99%

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Zhang

2016

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

With dramatic growth of data and rapid enhancement of computing powers, data accesses become the bottleneck restricting overall performance of a computer system. Emerging phase-change memory (PCM) is byte-addressable like DRAM, persistent like hard disks and Flash SSD, and about four orders of magnitude faster than hard disks or Flash SSDs for typical file system I/Os. The maturity of PCM from research to production provides a new opportunity for improving the I/O performance of a system. However, PCM also has some weaknesses, for example, long write latency, limited write endurance, and high active energy. Existing processor cache systems, main memory systems, and online storage systems are unable to leverage the advantages of PCM, and/or to mitigate PCM's drawbacks. The reason behind this incompetence is that they are designed and optimized for SRAM, DRAM memory, and hard drives, respectively, instead of PCM memory. There have been some efforts concentrating on rethinking computer architectures and software systems for PCM. This article presents a detailed survey and review of the areas of computer architecture and software systems that are oriented to PCM devices. First, we identify key technical challenges that need to be addressed before this memory technology can be leveraged, in the form of processor cache, main memory, and online storage, to build high-performance computer systems. Second, we examine various designs of computer architectures and software systems that are PCM aware. Finally, we obtain several helpful observations and propose a few suggestions on how to leverage PCM to optimize the performance of a computer system. ACM Reference Format:Chengwen Wu, Guangyan Zhang, and Keqin Li. 2016. Rethinking computer architectures and software systems for phase-change memory.

show abstract

Section: Reducing Wear On Pcmmentioning

confidence: 99%

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Zhang

2016

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…In order to overcome PCM's limited endurance, prior works have looked at better wear-leveling algorithms [Qureshi et al 2009a], reducing write traffic to PCM memory through partial writes ], writing select bits [Cho and Lee 2009;Zhang and Li 2009], randomizing data placement [Seong et al 2010a], exploring intelligent writes [Chen et al 2012a], and using DRAM buffers [Qureshi et al 2009b]. All of these techniques focus on applying their optimizations prior to the first bit failure.…”

Section: Pcm Based Main Memory and Wear-out Problemmentioning

confidence: 99%

Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks

Chen

Venkataramani

Huang

2014

J. Emerg. Technol. Comput. Syst.

Self Cite

View full text Add to dashboard Cite

DRAM technology challenges have increased the necessity to adapt to the emerging memory technologies like Phase-Change Memory (PCM or PRAM). While such emerging technologies provide benefits like storage density, nonvolatility, and low energy consumption, they are constrained by limited write endurance that becomes more pronounced with process variation. In this article, we explore a novel PRAM-based main memory system which resuscitates a group of faulty pages in a cost-effective manner to significantly extend the PCM main memory lifetime while minimizing the performance impact. In particular, we explore three different dimensions of dynamic redundancy levels and group sizes, and design low-cost hardware and software support for our proposed schemes. We aim to have minimal hardware modifications (that have less than 1% on-chip and off-chip area overheads). Also, our schemes can improve the PRAM lifetime by up to 105× (times) over a chip with no error correction capabilities, and outperform prior schemes such as DRM and ECP at a small fraction of the hardware cost. The performance overhead resulting from our scheme is less than 8% on average across 21 applications from SPEC2006, Splash-2, and PARSEC benchmark suites.

show abstract

“…The common focus of all these works is using instrumentation techniques and platform monitoring to understand how specific workloads use memory. With emerging memory technologies [8] [18] [19] [20] having different properties from conventional DRAM that has been used for the past decade, this type of characterization focus becomes particularly important.…”

Section: Related Work a Memory System Characterizationmentioning

confidence: 99%

Memory system characterization of big data workloads

Dimitrov¹,

Kumar²,

et al. 2013

2013 IEEE International Conference on Big Data

View full text Add to dashboard Cite

Two recent trends that have emerged include (1) Rapid growth in big data technologies with new types of computing models to handle unstructured data, such as mapreduce and noSQL (2) A growing focus on the memory subsystem for performance and power optimizations, particularly with emerging memory technologies offering different characteristics from conventional DRAM (bandwidths, read/write asymmetries).This paper examines how these trends may intersect by characterizing the memory access patterns of various Hadoop and noSQL big data workloads. Using memory DIMM traces collected using special hardware, we analyze the spatial and temporal reference patterns to bring out several insights related to memory and platform usages, such as memory footprints, read-write ratios, bandwidths, latencies, etc. We develop an analysis methodology to understand how conventional optimizations such as caching, prediction, and prefetching may apply to these workloads, and discuss the implications on software and system design.

show abstract

Energy-aware writes to non-volatile main memory

Cited by 36 publications

References 11 publications

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks

Memory system characterization of big data workloads

Contact Info

Product

Resources

About