Energy Efficiency and Yield Optimization for Optical Interconnects via Transceiver Grouping

Abstract

Optical interconnects enabled by silicon microringbased transceivers offer great potential for short-reach data communication in future high-performance computing systems. However, microring resonators are prone to process variations that harm both the energy efficiency and the yield of the fabricated transceivers. Especially in the application scenario where a batch of transceivers are fabricated for assembling multiple optical networks, how the transceivers are mixed and matched can directly impact the average energy efficiency and the yield of the networks assembled. In this study, we propose transceiver grouping for assembling communication networks from a pool of fabricated transceivers, aiming to optimize the network energy efficiency and the yield. We evaluated our grouping algorithms by wafer-scale measurement data of microring-based transceivers, as well as synthetic data generated based on an experimentally validated variation model. Our experimental results demonstrate that optimized grouping achieves significant improvement in the network energy efficiency and the yield across a wide range of network configurations, compared to a baseline strategy that randomly groups the transceivers.

Process Variation-Aware Compact Model of Strip Waveguides for Photonic Circuit Simulation

“…As the FSR is increased, the average per sample error in both cases improves steadily until it reaches the aforementioned floor. This is consistent with (19), indicating that a larger FSR corresponds to a wider margin of error for the fringe order estimate. For both the naïve and bias compensation methods, there is a critical FSR value beyond which the fringe order is correctly estimated for all samples.…”

“…Yield is a ubiquitous metric used across semiconductor manufacturing, with improvements in yield being strongly correlated with reductions in the time and costs associated with PIC design cycles [15]- [17]. The need for predictive yield models can be mitigated to some degree by designing variation-robust devices [18] or PICs such that performance variations can be tolerated or corrected for post fabrication [19], [20]. In each of these cases, however, quantitative yield data cannot be determined prior to fabrication-an obstacle that will be exacerbated as the number of components per PIC in silicon is projected to scale well into the millions within the next decade [21].…”

Scalable architecture for sub-pJ/b multi-Tbps comb-driven DWDM silicon photonic transceiver

“…76 test structures whose key performance metrics-including their sensitivity to process variations and thermal fluctuations-are closely correlated to their corresponding intra-link counterparts due to spacial proximity. 69,70 In addition to enabling this post-fabrication and pre-packaging qualitative analysis, we also incorporated a number of variation-aware design choices at both device and system levels for maximizing the likelihood of the proposed architecture resulting in the greatest possible performance and yield despite being subject to wafer-scale process variations and runtime thermal fluctuations.…”